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1. 发明专利

JPH0562349B2 失效
公开(公告)号：JPH0562349B2
公开(公告)日：1993-09-08
申请号：JP7443184
申请日：1984-04-13
申请人： ASCII CORP , YAMAHA CORP
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RYOZO , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/00 , G09G5/36

2. 发明专利

JPH0562346B2 失效
公开(公告)号：JPH0562346B2
公开(公告)日：1993-09-08
申请号：JP11161384
申请日：1984-05-31
申请人： ASCII CORP , YAMAHA CORP
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RYOZO , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU
IPC分类号： H04N9/65 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/06

3. 发明专利

JPH0569224B2 失效
公开(公告)号：JPH0569224B2
公开(公告)日：1993-09-30
申请号：JP5512885
申请日：1985-03-19
申请人： ASCII CORP , YAMAHA CORP
发明人： ISHII TAKATOSHI , KANEKO MAKOTO
IPC分类号： G09G5/02 , G09G5/06 , G09G5/08
摘要： A display controller can display a cursor having sufficient contour irrespective of the background color. The display controller has two cursor pattern memories from which first and second cursor patterns are read in such a timing that the first cursor pattern is displayed at a selected position on the screen and that the second cursor pattern is superimposed on the first cursor pattern. The display controller also has two registers storing therein first and second color codes corresponding respectively to the first and second cursor patterns. The color of the first cursor pattern is determined by a color code obtained by subjecting the first color code and a background color code read from a video memory to a logical multiplication, and the color of the second cursor pattern is determined by a color code obtained by subjecting the color code of the first cursor pattern and the second color code to an exclusive-OR operation. The logical operations are selectively effected in accordance with two control bits stored in a register.

4. 发明专利

JPH0562351B2 失效
公开(公告)号：JPH0562351B2
公开(公告)日：1993-09-08
申请号：JP10609184
申请日：1984-05-25
申请人： ASCII CORP , YAMAHA CORP
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RYOZO , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU , MORIMOTO MINORU
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G1/28 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/395

5. 发明专利

JPH0562350B2 失效
公开(公告)号：JPH0562350B2
公开(公告)日：1993-09-08
申请号：JP10609084
申请日：1984-05-25
申请人： ASCII CORP , YAMAHA CORP
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RYOZO , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU , MORIMOTO MINORU
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G1/28 , G09G5/00 , G09G5/06 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/395

9. 发明专利

JPH02162396A CHARACTER PATTERN GENERATING METHOD 失效
公开(公告)号：JPH02162396A
公开(公告)日：1990-06-21
申请号：JP31822888
申请日：1988-12-16
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/26 , G09G5/24
摘要： PURPOSE:To process characters of high quality fast by providing a display memory with 1-bit capacity for each picture element of a display screen and a one-line buffer, storing the contours of character patterns as character information and generating picture element data with the character information and buffer data. CONSTITUTION:A pattern generating device consists of a CPU 11, a display controller 12, a display pattern modifying circuit 13, a monitor 14 for screen display such as a CRT, and a display memory device 15 which is stored with the character information for character pattern generation. The memory 15 is provided with 1 bit capacity and stored with the contours of character patterns as the character information. Further, the line buffer 4 is incorporated in the circuit 13 and data corresponding to 1st - (m)th picture elements are stored in (0)-th - (m-1)th addresses. The output of a logic gate 22 is inputted to an FF 23, which outputs the buffer data. Thus, one picture element is made to corresponding to 1-bit character information and the start point, end point, internal painting-out points, etc., of the patterns are determined.

10. 发明专利

JPH02154295A COLOR DISPLAY DEVICE 失效
公开(公告)号：JPH02154295A
公开(公告)日：1990-06-13
申请号：JP30863788
申请日：1988-12-06
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/06 , G09G5/00
摘要： PURPOSE:To overlap RGB data by providing a priority circuit which preferencially outputs either the RGB data of other circuit supplied to input terminals or that which is outputted from a look-up table. CONSTITUTION:The RGB data from an exterior circuit is supplied to the input terminal B in the priority circuit 4 through an input/output terminal Ta. When a color code of 8 bits is supplied from a multiplexer 2, the look-up table 1 supplies the RGB data of 18 bits corresponding to the one to the input terminal A in the priority circuit 4. A controller 3 is controlled by data DB0-DB7 supplied from the exterior circuit (host side) and the priority circuit 4 preferentially outputs th RGB data which is a side displayed by a controlling signal Sc. Other than rewriting, the multiplexer 2 selects color codes PA0-PA7 read out from a VRAM (video RAM). Thus, the overlapping of the RGB data picture can be carried out.

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