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1. 发明申请

US20130234285A1 INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON 审中-公开
公开(公告)号：US20130234285A1
公开(公告)日：2013-09-12
申请号：US13681013
申请日：2012-11-19
申请人： NEC ELECTRONICS CORPORATION
发明人： Kenichiro HIJIOKA , Akira TANABE , Yoshihiro HAYASHI
IPC分类号： H01L49/02
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/34 , H01F41/041 , H01F2017/002 , H01F2017/004 , H01F2017/0086 , Y10T29/4902 , Y10T29/49071
摘要： An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

2. 发明申请

US20110062585A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110062585A1
公开(公告)日：2011-03-17
申请号：US12805511
申请日：2010-08-03
申请人： Takekazu TANAKA , Kouhei TAKAHASHI , Seiji OKABE
发明人： Takekazu TANAKA , Kouhei TAKAHASHI , Seiji OKABE
IPC分类号： H01L23/49
CPC分类号： H01L24/05 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L2224/02166 , H01L2224/04042 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/32225 , H01L2224/32245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/48507 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/01203 , H01L2924/01327 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20755 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/013 , H01L2924/00012 , H01L2924/2075 , H01L2924/20754 , H01L2924/01006
摘要： A semiconductor device includes a semiconductor chip, an electrode pad provided in the semiconductor chip, in which the electrode pad includes Al as a major constituent and further includes Cu, a coupling member coupled to the electrode pad, in which the coupling member primarily includes Cu, a plurality of layers of Cu and Al alloys formed between the electrode pad and the coupling member, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, in which the encapsulating resin encapsulates the semiconductor chip, the electrode pad, and the coupling member. The plurality of layers of Cu and Al alloys includes a CuAl2 layer formed on the electrode pad, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.
摘要翻译：半导体器件包括半导体芯片，设置在半导体芯片中的电极焊盘，其中电极焊盘包括Al作为主要成分，并且还包括耦合到电极焊盘的Cu，耦合部件主要包括Cu 形成在电极焊盘和耦合部件之间的多层Cu和Al合金，以及封装树脂，其包含小于或等于1000ppm的卤素，其中封装树脂封装在半导体芯片上，电极焊盘，以及联接构件。多层Cu和Al合金包括形成在电极焊盘上的CuAl2层，形成在CuAl2层上的CuAl层，以及包含在CuAl层上形成的Cu9Al4和Cu3Al2之一的层。

3. 发明申请

US20110051576A1 Optical disk device 有权
公开(公告)号：US20110051576A1
公开(公告)日：2011-03-03
申请号：US12801427
申请日：2010-06-08
申请人： Tetsuo Ashizawa , Hiromi Honma
发明人： Tetsuo Ashizawa , Hiromi Honma
IPC分类号： G11B20/10 , G11B27/36
CPC分类号： G11B20/10333 , G11B20/10046 , G11B20/10212 , G11B20/10425 , G11B2020/1287 , G11B2220/2537
摘要： An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.

4. 发明申请

US20110051541A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20110051541A1
公开(公告)日：2011-03-03
申请号：US12801652
申请日：2010-06-18
申请人： Akihiro Banno
发明人： Akihiro Banno
IPC分类号： G11C29/00 , G11C8/18
CPC分类号： G11C29/06 , G11C29/18 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.
摘要翻译：包括以矩阵模式布置的多个存储单元的半导体器件，与时钟同步地将写入数据写入存储器单元的写入放大器，读出与存储器单元同步的写入数据的读出放大器时钟，多个列选择开关，其将多个存储单元连接到读出放大器和写放大器;列地址解码器，使得与多个存储单元中的一列相对应的列选择开关为导通状态基于列地址的行地址解码器，其基于行地址来激活一行的存储单元;以及测试写入电路，其基于测试模式信号将对应于测试信号的逻辑电平的数据写入存储单元。

5. 发明申请

US20110050342A1 Push-pull amplifier circuit and operational amplifier circuit using the same 有权
标题翻译：推挽放大电路和运算放大器电路使用相同
公开(公告)号：US20110050342A1
公开(公告)日：2011-03-03
申请号：US12805265
申请日：2010-07-21
申请人： Tachio Yuasa
发明人： Tachio Yuasa
IPC分类号： H03F3/45 , H03F3/26
CPC分类号： H03F3/3022 , H03F3/45183 , H03F2203/45632 , H03F2203/45674
摘要： A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor.
摘要翻译：包括第一至第三电流路径的推挽放大器。第一电流路径包括允许第一电流根据输入信号流过第一电流路径的第一晶体管。第二电流路径包括允许与第一电流相反相位的第二电流根据第一电流流过第二电流路径的第二晶体管; 第一电阻; 所述第三晶体管连接到所述第一电阻器的一端并且具有连接到所述第一电阻器的另一端的控制端子。第三电流路径包括输出端子; 第四晶体管，其允许具有与所述第一电流相同相位的电流根据所述输入信号流过所述第三电流路径; 以及第五晶体管，其允许具有与第二电流相同相位的电流根据第一电阻器和第三晶体管之间的第一节点的电压流过第三电流路径。

6. 发明申请

US20110032004A1 Light-receving circuit and semiconductor device having same 有权
标题翻译：光接收电路和具有该光接收电路的半导体器件
公开(公告)号：US20110032004A1
公开(公告)日：2011-02-10
申请号：US12805049
申请日：2010-07-08
申请人： Hitoshi Imai
发明人： Hitoshi Imai
IPC分类号： H02M11/00
CPC分类号： H01L31/02019 , G11B7/13 , H03F3/087
摘要： A light-receiving circuit includes a photodiode that converts an input optical signal to a current signal; a current-voltage converting circuit that outputs an output voltage signal obtained by adding a reference voltage to a voltage signal proportional to the current value of the current signal; and an input current limiting unit that supplies the current-voltage converting circuit with the current signal upon limiting the current value of this current signal based upon the reference voltage in such a manner that the output voltage signal will not exceed a constant value irrespective of the value of the reference voltage.
摘要翻译：光接收电路包括将输入光信号转换为电流信号的光电二极管; 电流电压转换电路，输出通过将参考电压加到与当前信号的当前值成比例的电压信号上而获得的输出电压信号; 以及输入电流限制单元，其基于所述参考电压限制所述电流信号的电流值，使所述电流 - 电压转换电路提供所述电流信号，使得所述输出电压信号不会超过常数值，而不管参考电压值。

7. 发明申请

US20110029757A1 STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF 审中-公开
标题翻译：流处理器及其任务管理方法
公开(公告)号：US20110029757A1
公开(公告)日：2011-02-03
申请号：US12825868
申请日：2010-06-29
申请人： Hiroyuki NAKAJIMA
发明人： Hiroyuki NAKAJIMA
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3877
摘要： A stream processor includes a programmable main processor MP, and a coprocessor CP that executes an extension instruction, the extension instruction being different from a basic instruction executed by the main processor MP. The main processor MP includes a coprocessor controller CPC outputting the extension instruction to the coprocessor CP, and the coprocessor CP includes a task controller TC, the task controller controlling a task performed based on the extension instruction and outputting status information ST of the task on every clock. The coprocessor controller CPC controls the coprocessor CP based on the status information ST and a basic instruction executed by the main processor MP in background in advance.
摘要翻译：流处理器包括可编程主处理器MP和执行扩展指令的协处理器CP，该扩展指令与由主处理器MP执行的基本指令不同。主处理器MP包括将辅助处理器CP输出到协处理器CP的协处理器控制器CPC，并且协处理器CP包括任务控制器TC，任务控制器控制基于扩展指令执行的任务，并且在每一个上输出任务的状态信息ST 时钟。协处理器控制器CPC预先根据状态信息ST和由主处理器MP执行的基本指令来控制协处理器CP。

8. 发明申请

US20110026572A1 BAUD RATE ERROR DETECTION CIRCUIT AND BAUD RATE ERROR DETECTION METHOD 审中-公开
标题翻译：波特率误差检测电路和波特率误差检测方法
公开(公告)号：US20110026572A1
公开(公告)日：2011-02-03
申请号：US12822887
申请日：2010-06-24
申请人： Takashi Kitahara
发明人： Takashi Kitahara
IPC分类号： H04B17/00
CPC分类号： H04L7/044 , H04L7/04
摘要： A baud rate error detection circuit has an edge detector, a start bit sampling circuit and an abnormal waveform detection circuit. The edge detector receives sync-field used for adjusting a baud rate of serial communication, and generates an edge detection signal in response to an edge included in the sync-field. The start bit sampling circuit measures a bit width of a start bit of the sync-field based on the edge detection signal and an internal clock signal, and generates an expected value signal indicating the bit width of the start bit as an expected value. The abnormal waveform detection circuit measures an inter-edge width after the start bit based on the edge detection signal and the internal clock signal, and generates an abnormal waveform detection signal if an error between the inter-edge width and the expected value indicated by the expected value signal exceeds a predetermined allowable error range.
摘要翻译：波特率误差检测电路具有边缘检测器，起始位采样电路和异常波形检测电路。边缘检测器接收用于调整串行通信的波特率的同步字段，并且响应于包括在同步字段中的边缘产生边缘检测信号。起始比特采样电路基于边缘检测信号和内部时钟信号来测量同步场的开始位的位宽，并且产生指示起始位的位宽度的期望值信号作为期望值。异常波形检测电路基于边沿检测信号和内部时钟信号测量起始位之后的边缘间宽度，并且如果边缘间宽度与由所述边缘检测信号指示的期望值之间的误差产生异常波形检测信号期望值信号超过预定的允许误差范围。

9. 发明申请

US20110024826A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110024826A1
公开(公告)日：2011-02-03
申请号：US12827015
申请日：2010-06-30
申请人： HIROAKI MIZUSHIMA , FUMIHIKO HAYASHI
发明人： HIROAKI MIZUSHIMA , FUMIHIKO HAYASHI
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7881 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other.
摘要翻译：非易失性半导体存储器件包括第一柱状突起和形成为在半导体衬底的表面上间隔开的第二柱状突起，并且第一和第二柱状突起各自包括分裂门非易失性存储单元，其中第一源极/ 漏极区域和第二源极/漏极区域形成在周围部分和末端，并且其中层叠电荷累积膜和存储栅极线的第一层状结构和第二层状结构，其中栅极氧化膜和控制栅极线分别形成在周围部分和末端之间的侧壁的表面上。第一层状结构也形成在第一和第二柱状突起之间，由此第一柱状突起的存储栅极线和第二柱状突起彼此连接。

10. 发明申请

US20110018576A1 METHOD AND DEVICE FOR TESTING SEMICONDUCTOR 审中-公开
标题翻译：用于测试半导体的方法和装置
公开(公告)号：US20110018576A1
公开(公告)日：2011-01-27
申请号：US12818857
申请日：2010-06-18
申请人： Yoshiaki MAKINO
发明人： Yoshiaki MAKINO
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2889 , G01R19/0092 , G01R31/2608 , G01R31/2839
摘要： A semiconductor testing device of the prevent invention includes a current detecting circuit, an electric current drawing circuit, and a determining device. The electric current drawing circuit is connected to a semiconductor device under test, and draws a branched electric current branched from a measured electric current output from a second terminal based on predetermined electric voltage. The current detecting circuit is connected to the semiconductor device, and detects a detection current obtained by subtracting the branched electric current from the measured electric current. The determining device determines a quality of the semiconductor device based on the detection current.
摘要翻译：防止发明的半导体测试装置包括电流检测电路，电流描绘电路和确定装置。电流引入电路连接到被测半导体器件，并且根据预定的电压从第二端子输出的测量电流中抽出分支的电流。电流检测电路连接到半导体器件，并且检测通过从测量的电流中减去分支电流而获得的检测电流。确定装置基于检测电流来确定半导体器件的质量。

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