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91. 发明授权

US09613867B2 Symmetric tunnel field effect transistor 有权
公开(公告)号：US09613867B2
公开(公告)日：2017-04-04
申请号：US15084137
申请日：2016-03-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Mohit Bajaj , Suresh Gundapaneni , Aniruddha Konar , Narasimha R. Mavilla , Kota V. R. M. Murali , Edward J. Nowak
IPC分类号： H01L21/8234 , H01L21/3115 , H01L29/66 , H01L21/02 , H01L21/8232 , H01L29/786
CPC分类号： H01L29/41725 , H01L21/02414 , H01L21/02483 , H01L21/02565 , H01L21/02581 , H01L21/3115 , H01L21/8232 , H01L21/823418 , H01L29/0653 , H01L29/083 , H01L29/0834 , H01L29/0847 , H01L29/161 , H01L29/205 , H01L29/24 , H01L29/267 , H01L29/66795 , H01L29/66977 , H01L29/7391 , H01L29/772 , H01L29/78 , H01L29/785 , H01L29/78681 , H01L29/7869 , H01L29/78693
摘要： The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

92. 发明申请

US20160380095A1 HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION 审中-公开
标题翻译：具有形状的DRIFT区域的高电压FinFET结构
公开(公告)号：US20160380095A1
公开(公告)日：2016-12-29
申请号：US14750476
申请日：2015-06-25
申请人： International Business Machines Corporation
发明人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0847 , H01L29/1095 , H01L29/4238 , H01L29/66545 , H01L29/66803 , H01L29/66818 , H01L29/7835 , H01L29/785
摘要： Devices and methods for a high voltage FinFET with a shaped drift region include a lateral diffusion metal oxide semiconductor (LDMOS) FinFET having a substrate with a top surface and a fin attached to the top surface. This fin includes a source region having a first type of doping, an undoped gate-control region adjacent the source region, a drift region adjacent the undoped gate-control region opposite the source region, and a drain region. The amount of doping of the source region is greater than the amount in the drift region. The drain region has the same type of doping and is adjacent the drift region. The fin in the drift region is tapered, being wider closest to the undoped gate-control region and thinner closest to the drain region. A gate stack is attached to the top surface of the substrate and located with the undoped gate-control region.
摘要翻译：具有成形漂移区域的高电压FinFET的装置和方法包括具有顶部表面的衬底和附接到顶表面的鳍的横向扩散金属氧化物半导体（LDMOS）FinFET。该散热片包括具有第一种掺杂的源极区域，与源极区域相邻的未掺杂栅极控制区域，与源极区域相对的未掺杂栅极控制区域附近的漂移区域和漏极区域。源极区域的掺杂量大于漂移区域中的量。漏区具有相同类型的掺杂并且与漂移区相邻。漂移区域中的翅片是渐缩的，最接近未掺杂的栅极控制区域更宽并且更靠近漏极区域。栅极堆叠被附着到衬底的顶表面并且与未掺杂的栅极控制区域一起定位。

93. 发明授权

US09419016B2 Junctionless tunnel FET with metal-insulator transition material 有权
标题翻译：具有金属 - 绝缘体过渡材料的无结隧道FET
公开(公告)号：US09419016B2
公开(公告)日：2016-08-16
申请号：US14537188
申请日：2014-11-10
申请人： International Business Machines Corporation
发明人： Mohit Bajaj , Suresh Gundapaneni , Aniruddha Konar , Kota V. R. M. Murali , Edward J. Nowak
IPC分类号： H01L29/02 , H01L27/12 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/10 , H01L21/84 , H01L21/02
CPC分类号： H01L29/66977 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/1033 , H01L29/42364 , H01L29/42372 , H01L29/4908 , H01L29/511 , H01L29/517 , H01L29/66795 , H01L29/7855 , H01L29/78645 , H01L29/78648 , H01L49/003
摘要： Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.
摘要翻译：本公开的实施例提供集成电路（IC）结构，其可以包括：具有基本上均匀的掺杂分布的掺杂半导体层; 位于所述掺杂半导体层上的第一栅极结构; 以及位于所述掺杂半导体层上的第二栅极结构，所述第二栅极结构包括金属 - 绝缘体转变材料和将所述金属 - 绝缘体转变材料与所述掺杂半导体层分离的栅极电介质层。

94. 发明授权

US09373641B2 Methods of forming field effect transistors using a gate cut process following final gate formation 有权
标题翻译：在最终栅极形成之后使用栅极截止工艺形成场效应晶体管的方法
公开(公告)号：US09373641B2
公开(公告)日：2016-06-21
申请号：US14462631
申请日：2014-08-19
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762 , H01L21/8234 , H01L29/66 , H01L21/3105 , H01L29/51 , H01L27/088 , H01L29/06 , H01L21/265 , H01L29/49
CPC分类号： H01L21/28123 , H01L21/265 , H01L21/26513 , H01L21/31053 , H01L21/762 , H01L21/76283 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L21/845 , H01L23/528 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6681
摘要： Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.
摘要翻译：公开了使用最终栅极切割工艺和所得结构的场效应晶体管（FET）形成方法。一种方法分别在第一和第二半导体本体上形成用于第一和第二FET的细长栅极。在半导体体之间的细长栅极的一部分上形成开口，至少切割栅极导体层。开口填充有隔离层，从而形成隔离区域，其将细长栅极分别分成用于第一和第二FET的第一和第二栅极。另一种方法形成跨越细长半导体体的至少三个栅极。形成隔离区，其不仅通过栅极的中心一部分的一部分延伸，而且延伸穿过与该栅极相邻的细长半导体本体的对应部分，从而将细长半导体本体分成第一和第第二个FET。

95. 发明申请

US20160133648A1 JUNCTIONLESS TUNNEL FET WITH METAL-INSULATOR TRANSITION MATERIAL 有权
标题翻译：具有金属绝缘体过渡材料的无连接隧道FET
公开(公告)号：US20160133648A1
公开(公告)日：2016-05-12
申请号：US14537188
申请日：2014-11-10
申请人： International Business Machines Corporation
发明人： Mohit Bajaj , Suresh Gundapaneni , Aniruddha Konar , Kota V.R.M. Murali , Edward J. Nowak
IPC分类号： H01L27/12 , H01L29/51 , H01L21/02 , H01L29/10 , H01L21/84 , H01L29/66 , H01L29/423
CPC分类号： H01L29/66977 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/1033 , H01L29/42364 , H01L29/42372 , H01L29/4908 , H01L29/511 , H01L29/517 , H01L29/66795 , H01L29/7855 , H01L29/78645 , H01L29/78648 , H01L49/003
摘要： Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.
摘要翻译：本公开的实施例提供集成电路（IC）结构，其可以包括：具有基本上均匀的掺杂分布的掺杂半导体层; 位于所述掺杂半导体层上的第一栅极结构; 以及位于所述掺杂半导体层上的第二栅极结构，所述第二栅极结构包括金属 - 绝缘体转变材料和将所述金属 - 绝缘体转变材料与所述掺杂半导体层分离的栅极电介质层。

96. 发明授权

US09299835B1 Vertical field effect transistors 有权
标题翻译：垂直场效应晶体管
公开(公告)号：US09299835B1
公开(公告)日：2016-03-29
申请号：US14560672
申请日：2014-12-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L21/823487 , H01L21/28518 , H01L21/764 , H01L21/823418 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L27/088 , H01L29/0653 , H01L29/4238 , H01L29/42392 , H01L29/665 , H01L29/66666 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
摘要翻译：公开了具有最小间距和制造方法的垂直场效应晶体管（FET）。该结构包括至少一个垂直翅片结构和与至少一个垂直翅片结构接触的栅极材料。该结构还包括与至少一个垂直翅片的端部电接触的金属材料。

97. 发明授权

US09286425B2 Method, structure and design structure for customizing history effects of SOI circuits 有权
公开(公告)号：US09286425B2
公开(公告)日：2016-03-15
申请号：US13747798
申请日：2013-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/8238 , G06F17/50 , H01L21/762 , H01L21/84 , H01L27/12
CPC分类号： G06F17/5045 , H01L21/76229 , H01L21/84 , H01L27/1203
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

98. 发明授权

US09224837B2 Semiconductor structures with pair(s) of vertical field effect transistors, each pair having a shared source/drain region and methods of forming the structures 有权
公开(公告)号：US09224837B2
公开(公告)日：2015-12-29
申请号：US14711069
申请日：2015-05-13
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/72 , H01L29/66 , H01L29/78 , H01L21/308 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/66666 , H01L21/3086 , H01L21/823425 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/66484 , H01L29/7827 , H01L29/7831
摘要： Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).

99. 发明申请

US20150364534A1 NON-PLANAR CAPACITORS WITH FINELY TUNED CAPACITANCE VALUES AND METHODS OF FORMING THE NON-PLANAR CAPACITORS 有权
标题翻译：具有精细调谐电容值的非平面电容器和形成非平面电容器的方法
公开(公告)号：US20150364534A1
公开(公告)日：2015-12-17
申请号：US14306294
申请日：2014-06-17
申请人： International Business Machines Corporation
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L49/02 , H01L27/06 , H01L21/308 , H01L29/78 , H01L29/66
CPC分类号： H01L28/40 , H01L21/3086 , H01L21/845 , H01L27/0629 , H01L27/1207 , H01L28/60 , H01L28/91 , H01L29/66795 , H01L29/785
摘要： Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.
摘要翻译：公开了具有微调电容的非平面电容器及其形成方法。电容器各自包括一个或多个半导体本体和穿过一个或多个半导体主体的一个或多个栅极叠层。蚀刻至少一个第一半导体本体，使得其长度比其它半导体本体短，其被并入其它非平面器件和/或并入相同的非平面电容器中。此外，可以形成至少一个栅极堆叠，使得其穿过第一部分，特别是穿过缩短的半导体本体的端部，并且进一步使其横向延伸超过该第一部分一段距离。在这种电容器中，对应于电容器导体的电容器导体的对应于电容器电介质和另一个电容器导体的电容器导体的短路半导体本体的第一部分的长度被预先确定以获得所需的电容。

100. 发明授权

US09093478B1 Integrated circuit structure with bulk silicon FinFET and methods of forming 有权
标题翻译：集成电路结构采用散装硅FinFET及其成型方法
公开(公告)号：US09093478B1
公开(公告)日：2015-07-28
申请号：US14250725
申请日：2014-04-11
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ali Khakifirooz , Qizhi Liu , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/36 , H01L29/66 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10826 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. A method of forming an IC structure according to the present disclosure can include: forming a layered dummy structure on a bulk substrate, wherein the layered dummy structure includes: a first crystalline semiconductive layer; a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the second crystalline semiconductive layer comprises a material distinct from the first crystalline semiconductive layer; and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the same material as the first crystalline semiconductive layer; forming a semiconductor fin on the layered dummy structure, wherein the semiconductor fin comprises part of a finFET structure; and selectively removing the layered dummy structure to form a cavity between the bulk substrate and the semiconductor fin.
摘要翻译：本公开通常提供具有体硅片finFET的集成电路（IC）结构及其形成方法。根据本公开的形成IC结构的方法可以包括：在体基板上形成分层虚拟结构，其中所述分层虚拟结构包括：第一晶体半导体层; 位于所述第一晶体半导体层上的第二晶体半导体层，其中所述第二晶体半导体层包括与所述第一晶体半导体层不同的材料; 以及位于所述第二晶体半导体层上的第三晶体半导体层，其中所述第三晶体半导体层包含与所述第一晶体半导体层相同的材料; 在所述分层虚拟结构上形成半导体鳍片，其中所述半导体鳍片包括finFET结构的一部分; 并且选择性地去除分层虚拟结构以在体基板和半导体鳍之间形成空腔。

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