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1. 发明申请

US20190206880A1 METHOD FOR PRODUCING PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20190206880A1
公开(公告)日：2019-07-04
申请号：US16296564
申请日：2019-03-08
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Fujio MASUOKA , Nozomu HARADA
IPC分类号： H01L27/11 , H01L29/423 , H01L23/528 , H01L23/522 , H01L29/786 , H01L21/285 , H01L21/768
CPC分类号： H01L27/1104 , H01L21/28518 , H01L21/28531 , H01L21/76805 , H01L21/76831 , H01L23/5226 , H01L23/528 , H01L29/4238 , H01L29/42392 , H01L29/456 , H01L29/4966 , H01L29/7827 , H01L29/78642
摘要： A method for producing a semiconductor memory device includes forming two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.

2. 发明申请

US20190198670A1 FORMATION OF A BOTTOM SOURCE-DRAIN FOR VERTICAL FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：US20190198670A1
公开(公告)日：2019-06-27
申请号：US16289003
申请日：2019-02-28
申请人： International Business Machines Corporation
发明人： Marc A. Bergendahl , Kangguo Cheng , Fee Li Lie , Shogo Mochizuki , Junli Wang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7827 , H01L29/0847 , H01L29/41791 , H01L29/66545 , H01L29/66666 , H01L29/66795 , H01L29/785 , H01L29/78642
摘要： In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.

3. 发明申请

US20190198643A1 VERTICAL CHANNEL DEVICE AND METHOD OF FORMING SAME 审中-公开
公开(公告)号：US20190198643A1
公开(公告)日：2019-06-27
申请号：US16220361
申请日：2018-12-14
申请人： IMEC vzw
发明人： Boon Teik Chan , Anabela Veloso , Efrain Altamirano Sanchez , Zheng Tao
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78 , H01L21/3065
CPC分类号： H01L29/66666 , H01L21/3065 , H01L29/0847 , H01L29/42372 , H01L29/42392 , H01L29/6653 , H01L29/66742 , H01L29/7827 , H01L29/78642
摘要： The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer. Forming the vertical semiconductor structure includes: etching the upper semiconductor layer to form the upper portion and the intermediate semiconductor layer to form the intermediate portion, detecting whether the etching has reached the lower semiconductor layer, and in response to detecting that the etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during the etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form the lower portion. The modified etching chemistry is such that the lower portion is formed to present, along at least a part of the lower portion, a lateral dimension gradually increasing along a direction towards the substrate. The method further comprises forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.

4. 发明申请

US20190189790A1 METHOD AND STRUCTURE FOR FORMING IMPROVED SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS 审中-公开
公开(公告)号：US20190189790A1
公开(公告)日：2019-06-20
申请号：US16271069
申请日：2019-02-08
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Xin Miao , Wenyu Xu , Chen Zhang
IPC分类号： H01L29/76 , H01L29/66 , H01L29/786 , H01L29/423
CPC分类号： H01L29/7613 , H01L29/42392 , H01L29/66439 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

5. 发明申请

US20190115072A1 MULTI-STATE PHASE CHANGE MEMORY DEVICE WITH VERTICAL CROSS-POINT STRUCTURE 审中-公开
公开(公告)号：US20190115072A1
公开(公告)日：2019-04-18
申请号：US15869592
申请日：2018-01-12
申请人： SanDisk Technologies LLC
发明人： Federico Nardi , Christopher J. Petti , Gerrit Jan Hemink
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0092 , G11C2213/51 , G11C2213/52 , G11C2213/71 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/2427 , H01L27/2454 , H01L27/2463 , H01L27/249 , H01L29/78642 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

6. 发明申请

US20180337278A1 FORMING A COMBINATION OF LONG CHANNEL DEVICES AND VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE 审中-公开
公开(公告)号：US20180337278A1
公开(公告)日：2018-11-22
申请号：US16046123
申请日：2018-07-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cheng Chi , Tenko Yamashita , Chen Zhang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L21/8234 , H01L29/10 , H01L29/08 , H01L27/088 , H01L29/161
CPC分类号： H01L29/7827 , H01L21/823431 , H01L21/823456 , H01L21/823481 , H01L21/823487 , H01L27/088 , H01L27/0886 , H01L27/1207 , H01L27/1211 , H01L29/0847 , H01L29/42376 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66636 , H01L29/66666 , H01L29/66795 , H01L29/78 , H01L29/7856 , H01L29/78642
摘要： A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

7. 发明申请

US20180337133A1 MODULAR INTERCONNECTS FOR GATE-ALL-AROUND TRANSISTORS 审中-公开
公开(公告)号：US20180337133A1
公开(公告)日：2018-11-22
申请号：US15984263
申请日：2018-05-18
申请人： STMicroelectronics, Inc.
发明人： John H. Zhang
IPC分类号： H01L23/538 , H01L29/792 , H01L29/786 , H01L21/768 , H01L21/8238 , H01L29/78 , H01L29/775 , H01L29/66 , H01L29/423 , H01L29/417 , H01L29/16 , H01L29/06 , H01L27/092 , H01L27/07 , H01L27/06 , H01L27/02 , H01L27/11582 , H01L29/51
CPC分类号： H01L23/5386 , H01L21/76895 , H01L21/76897 , H01L21/823871 , H01L21/823885 , H01L23/5384 , H01L27/0255 , H01L27/0688 , H01L27/0705 , H01L27/0727 , H01L27/092 , H01L27/11582 , H01L29/0676 , H01L29/1608 , H01L29/41741 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/66742 , H01L29/775 , H01L29/7827 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

8. 发明申请

US20180301539A1 SEMICONDUCTOR DEVICES AND STRUCTURES AND METHODS OF FORMATION 审中-公开
公开(公告)号：US20180301539A1
公开(公告)日：2018-10-18
申请号：US16004908
申请日：2018-06-11
申请人： Micron Technology, Inc.
发明人： Gurtej S. Sandhu
IPC分类号： H01L29/49 , H01L29/786 , B82Y10/00 , H01L29/78 , H01L29/66 , H01L29/423 , H01L21/8234 , H01L29/40 , H01L29/24 , H01L27/12 , H01L27/105
CPC分类号： H01L29/7869 , B82Y10/00 , H01L21/823437 , H01L21/823487 , H01L27/105 , H01L27/1052 , H01L27/1225 , H01L29/24 , H01L29/401 , H01L29/42372 , H01L29/42392 , H01L29/49 , H01L29/4908 , H01L29/66666 , H01L29/66795 , H01L29/66969 , H01L29/7827 , H01L29/785 , H01L29/7855 , H01L29/78642 , H01L29/78648 , H01L29/78696
摘要： A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

9. 发明申请

US20180286869A1 VERTICAL GATE-ALL-AROUND TFET 审中-公开
公开(公告)号：US20180286869A1
公开(公告)日：2018-10-04
申请号：US15939108
申请日：2018-03-28
申请人： STMicroelectronics, Inc.
发明人： John H. ZHANG
IPC分类号： H01L27/108 , H01L45/00 , H01L21/28 , H01L21/8238 , B82Y10/00 , H01L33/04 , H01L31/0392 , H01L29/786 , H01L29/78 , H01L29/775 , H01L29/739 , H01L29/66 , H01L29/423 , H01L29/20 , H01L29/16 , H01L29/10 , H01L29/06 , H01L27/092 , H01L27/08 , H01L29/49
CPC分类号： H01L27/10879 , B82Y10/00 , H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L21/823885 , H01L21/823892 , H01L27/0814 , H01L27/092 , H01L27/0928 , H01L29/0653 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/42392 , H01L29/495 , H01L29/4966 , H01L29/66439 , H01L29/66666 , H01L29/66795 , H01L29/66909 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/7827 , H01L29/7855 , H01L29/7856 , H01L29/78618 , H01L29/78642 , H01L29/78696 , H01L31/0392 , H01L33/04 , H01L45/1233 , H01L2029/7858
摘要： A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

10. 发明申请

US20180277669A1 METHOD AND STRUCTURE FOR FORMING IMPROVED SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS 审中-公开
公开(公告)号：US20180277669A1
公开(公告)日：2018-09-27
申请号：US15464768
申请日：2017-03-21
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Xin Miao , Wenyu Xu , Chen Zhang
IPC分类号： H01L29/76 , H01L29/423 , H01L29/786 , H01L29/66
CPC分类号： H01L29/7613 , H01L29/42392 , H01L29/66439 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

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