专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US09397960B2 Packet steering 有权
标题翻译：包转向
公开(公告)号：US09397960B2
公开(公告)日：2016-07-19
申请号：US13291143
申请日：2011-11-08
申请人： Nir Haim Arad , Noam Bloch , Ariel Shahar , Hillel Chapman , Amir Wated
发明人： Nir Haim Arad , Noam Bloch , Ariel Shahar , Hillel Chapman , Amir Wated
IPC分类号： H04L12/931 , H04L12/54 , H04L12/721
CPC分类号： H04L45/74 , H04L45/38 , H04L45/745 , H04L47/10 , H04L49/351 , H04L49/355 , H04L49/358 , H04L49/70
摘要： A method for steering packets, including receiving a packet and determining parameters to be used in steering the packet to a specific destination, in one or more initial steering stages, based on one or more packet specific attributes. The method further includes determining an identity of the specific destination of the packet in one or more subsequent steering stages, governed by the parameters determined in the one or more initial stages and one or more packet specific attributes, and forwarding the packet to the determined specific destination.
摘要翻译：一种用于在一个或多个初始转向阶段中基于一个或多个分组特定属性来指导分组的方法，包括接收分组并确定要用于指导分组到特定目的地的参数。该方法还包括确定一个或多个后续转向级中的分组的特定目的地的身份，由在一个或多个初始阶段中确定的参数和一个或多个分组特定属性来管理，以及将分组转发到所确定的特定目的地。

92. 发明授权

US09298642B2 Sharing address translation between CPU and peripheral devices 有权
标题翻译：共享CPU和外围设备之间的地址转换
公开(公告)号：US09298642B2
公开(公告)日：2016-03-29
申请号：US13665946
申请日：2012-11-01
申请人： MELLANOX TECHNOLOGIES LTD.
发明人： Michael Kagan , Noam Bloch , Liran Liss , Shachar Raindel
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1081
摘要： A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.
摘要翻译：一种用于存储器访问的方法包括在主机操作系统在中央处理单元（CPU）上运行的主机操作系统的控制下维护主机存储器，用于由CPU执行的多个进程的各自的地址转换表。在外围设备中接收与给定进程相关联的工作项，在主机存储器中具有相应的地址转换表，并指定虚拟存储器地址时，外围设备将虚拟存储器地址转换为物理存储器地址通过访问主机存储器中给定进程的相应地址转换表。通过访问主机存储器中的物理存储器地址上的数据，在外围设备中执行工作项。

93. 发明授权

US09225628B2 Topology-based consolidation of link state information 有权
标题翻译：基于拓扑的整合链接状态信息
公开(公告)号：US09225628B2
公开(公告)日：2015-12-29
申请号：US13114071
申请日：2011-05-24
申请人： Eitan Zahavi
发明人： Eitan Zahavi
IPC分类号： H04L12/28 , H04L12/721 , H04L12/709 , H04L12/933
CPC分类号： H04L45/124 , H04L45/245 , H04L49/10 , Y02D50/30
摘要： A method in a network element that forwards packets to destination nodes includes identifying groups of the destination nodes. Respective performance metrics of multiple different candidate network paths, over which the destination nodes in a given group are reachable from the network element, are estimated jointly for all the destination nodes in the given group. A network path is selected from among the candidate network paths based on the estimated performance metrics. The packets addressed to the destination nodes in the given group are forwarded over the selected network path.
摘要翻译：将分组转发到目的地节点的网元中的方法包括识别目的节点的组。对于给定组中的所有目的地节点，可以联合估计多个不同候选网络路径的相应性能度量，通过该多个不同候选网络路径可以从给定组中的目的地节点到达网络元素。基于估计的性能度量，从候选网络路径中选择网络路径。寻址到给定组中的目的节点的数据包将通过所选网络路径转发。

94. 发明申请

US20150288624A1 LOW-LATENCY PROCESSING IN A NETWORK NODE 审中-公开
标题翻译：网络节点中的低延迟处理
公开(公告)号：US20150288624A1
公开(公告)日：2015-10-08
申请号：US14247255
申请日：2014-04-08
申请人： Mellanox Technologies Ltd.
发明人： Shachar Raindel , Yaniv Saar , Haggai Eran , Yishai Israel Hadas , Ari Zigler
IPC分类号： H04L12/861 , H04L29/08
CPC分类号： H04L49/90 , G06F13/382 , H04L49/9047
摘要： A method in a network node that includes a host and an accelerator, includes holding a work queue that stores work elements, a notifications queue that stores notifications of the work elements, and control indices for adding and removing the work elements and the notifications to and from the work queue and the notifications queue, respectively. The notifications queue resides on the accelerator, and at least some of the control indices reside on the host. Messages are exchanged between a network and the network node using the work queue, the notifications queue and the control indices.
摘要翻译：包括主机和加速器的网络节点中的方法包括保存存储工作元素的工作队列，存储工作元素的通知的通知队列，以及用于将工作元素和通知添加到和分别从工作队列和通知队列。通知队列驻留在加速器上，并且至少一些控制索引驻留在主机上。使用工作队列，通知队列和控制索引，在网络和网络节点之间交换消息。

95. 外观设计

USD734728S1 Connector module 有权
标题翻译：连接器模块
公开(公告)号：USD734728S1
公开(公告)日：2015-07-21
申请号：US29464186
申请日：2013-08-14
申请人： Mellanox Technologies Ltd.
设计人： Rafi Lagziel , Ori Ben David , Nimer Khazen

96. 发明授权

US08990472B2 Methods and systems for running network protocols over peripheral component interconnect express 有权
标题翻译：通过外围组件互连运行网络协议的方法和系统
公开(公告)号：US08990472B2
公开(公告)日：2015-03-24
申请号：US13658976
申请日：2012-10-24
申请人： Mellanox Technologies, Ltd.
发明人： Oren Tzvi Sela , Noam Bloch
IPC分类号： G06F13/42
CPC分类号： G06F13/4221 , G06F13/423 , G06F2213/0026
摘要： Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.
摘要翻译：披露了通过Peripheral Component Interconnect Express运行网络协议的方法和设备。方法和装置可以接收包括数据的电子信号。方法和设备还可以确定对应于从包括PCIe协议和网络协议的集合中选择的协议的数据。此外，方法和设备还可以基于所确定的协议来配置CPU。所述方法和设备还可以接收包括在CPU的引脚或引脚上的第二数据的第二电子信号，其中所述引脚或引脚连接到PCIe通道，并且其中根据所确定的协议对第二数据进行格式化。此外，方法和装置可以根据确定的协议处理第二数据。

97. 发明授权

US08959265B2 Reducing size of completion notifications 有权
标题翻译：减少完成通知的大小
公开(公告)号：US08959265B2
公开(公告)日：2015-02-17
申请号：US13682772
申请日：2012-11-21
申请人： Mellanox Technologies Ltd.
发明人： Ofer Hayut , Noam Bloch , Michael Kagan , Ariel Shachar
IPC分类号： G06F3/01 , G06F13/14
CPC分类号： G06F3/016 , G06F13/128 , G06F13/14
摘要： A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.
摘要翻译：计算机外围设备包括主机接口，其被配置为通过总线与主处理器和主机处理器的系统存储器进行通信。外围设备中的处理电路被配置为通过在主处理器上运行的客户端进程来接收和执行提交给外围设备的工作项目，并且响应于完成工作项目的执行，将完成报告写入系统存储器，包括首先完成报告第一数据大小和第二数据大小的第二完成报告，其小于第一数据大小。

98. 发明授权

US08924605B2 Efficient delivery of completion notifications 有权
公开(公告)号：US08924605B2
公开(公告)日：2014-12-30
申请号：US13682773
申请日：2012-11-21
申请人： Mellanox Technologies Ltd.
发明人： Ofer Hayut , Noam Bloch , Michael Kagan , Ariel Shachar
IPC分类号： G06F3/00 , G06F13/00 , G06F3/01 , H04L12/00 , H04L12/46
CPC分类号： G06F3/016 , G06F13/00 , H04L12/00 , H04L12/4641
摘要： A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction.

99. 发明申请

US20140369651A1 INTEGRATED OPTICAL COOLING CORE FOR OPTOELECTRONIC INTERCONNECT MODULES 有权
标题翻译：用于光电互连模块的集成光学冷却芯
公开(公告)号：US20140369651A1
公开(公告)日：2014-12-18
申请号：US14294167
申请日：2014-06-03
申请人： Mellanox Technologies Ltd.
发明人： Ori Ben David , Avner Badihi , Mordi Farkash , Kfir Katz
IPC分类号： G02B6/42
CPC分类号： G02B6/4268 , G02B6/4204 , G02B6/421 , G02B6/4214 , G02B6/423 , G02B6/4246 , G02B6/4249 , G02B6/4269 , G02B6/4271 , G02B6/4292 , G02B6/43 , Y10T29/49117
摘要： An apparatus includes one or more optoelectronic transducers, driving circuitry, one or more cooling elements, and a light coupling module. The optoelectronic transducers are configured to convert between optical signals conveyed over optical fibers and respective electrical signals. The driving circuitry is configured to process the electrical signals. The cooling elements are configured to remove heat that is produced at least by the driving circuitry. The light coupling module is configured to couple the optical signals between the optical fibers and the optoelectronic transducers, and additionally serves as a baseplate for the cooling elements.
摘要翻译：一种装置包括一个或多个光电换能器，驱动电路，一个或多个冷却元件和光耦合模块。光电子传感器被配置为在通过光纤传送的光信号和相应的电信号之间进行转换。驱动电路被配置为处理电信号。冷却元件构造成去除至少由驱动电路产生的热量。光耦合模块被配置为耦合光纤和光电换能器之间的光信号，并且另外用作冷却元件的基板。

100. 发明授权

US08914458B2 Look-ahead handling of page faults in I/O operations 有权
标题翻译：在I / O操作中提前处理页面错误
公开(公告)号：US08914458B2
公开(公告)日：2014-12-16
申请号：US13628075
申请日：2012-09-27
申请人： Mellanox Technologies Ltd.
发明人： Shachar Raindel , Haggai Eran , Liran Liss , Noam Bloch
IPC分类号： G06F15/167
CPC分类号： G06F3/067 , G06F3/061 , G06F3/0656 , G06F3/0659
摘要： A method for data transfer includes receiving in an input/output (I/O) operation a first segment of data to be written to a specified virtual address in a host memory. Upon receiving the first segment of the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. At least one second page of the host memory is identified, to which a second segment of the data is expected to be written. Responsively to detecting that the first page is swapped out and to identifying the at least one second page, at least the first and second pages are swapped into the host memory. After swapping at least the first and second pages into the host memory, the data are written to the first and second pages.
摘要翻译：一种用于数据传输的方法包括在输入/输出（I / O）操作中接收要写入主机存储器中的指定虚拟地址的第一数据段。在接收到数据的第一段时，检测到包含指定虚拟地址的第一页被转换出主机存储器。标识主机存储器的至少一个第二页，期望数据的第二段被写入到其上。响应于检测到第一页面被换出并且识别至少一个第二页面，至少第一页面和第二页面被交换到主机存储器中。至少将第一页和第二页交换到主机存储器之后，数据被写入第一页和第二页。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式