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91. 发明申请

US20190004985A1 FLASH-DRAM HYBRID MEMORY MODULE 审中-公开
公开(公告)号：US20190004985A1
公开(公告)日：2019-01-03
申请号：US15934416
申请日：2018-03-23
申请人： Netlist, Inc.
发明人： Hyun Lee , Chi-She Chen , Jeffrey C. Solomon , Scott H. Milton , Jayesh Bhakta
IPC分类号： G06F13/28 , G06F12/02 , G06F13/40 , G06F3/06 , G06F1/18 , G06F13/42 , G06F12/06 , G06F13/16 , G11C14/00 , G11C7/10
摘要： A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

92. 发明授权

US09996284B2 Non-volatile memory storage for multi-channel memory system 有权
公开(公告)号：US09996284B2
公开(公告)日：2018-06-12
申请号：US15255894
申请日：2016-09-02
申请人： NetList, Inc.
发明人： Hyun Lee
IPC分类号： G06F3/06 , G06F12/0815
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0653 , G06F3/0685 , G06F12/0246 , G06F12/0815 , G06F12/0868 , G06F2212/214 , G06F2212/621
摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

93. 发明申请

US20180113614A1 DIRECT DATA MOVE BETWEEN DRAM AND STORAGE ON A MEMORY MODULE 审中-公开
公开(公告)号：US20180113614A1
公开(公告)日：2018-04-26
申请号：US15665246
申请日：2017-07-31
申请人： NETLIST, INC.
发明人： Hyun Lee , Sheng Wang
IPC分类号： G06F3/06 , G06F13/16 , G06F13/40
CPC分类号： G06F3/061 , G06F3/0644 , G06F3/0646 , G06F3/0656 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F12/08 , G06F12/0897 , G06F13/1668 , G06F13/4068
摘要： A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.

94. 发明申请

US20180095908A1 MEMORY MODULE WITH TIMING-CONTROLLED DATA PATHS IN DISTRIBUTED DATA BUFFERS 审中-公开
公开(公告)号：US20180095908A1
公开(公告)日：2018-04-05
申请号：US15820076
申请日：2017-11-21
申请人： Netlist, Inc.
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F13/16 , G11C8/18 , G06F3/06
CPC分类号： G06F13/1673 , G06F1/10 , G06F3/0613 , G06F3/0647 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F13/1642 , G06F13/28 , G06F13/4027 , G11C5/04 , G11C7/1006 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/20 , G11C8/12 , G11C8/18 , G11C16/00 , G11C29/023 , G11C29/028 , G11C2029/0407
摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit includes a data path corresponding to each data signal line in the corresponding set of data/strobe signal lines, and a command processing circuit configured to decode module control signals from the module control circuit and to control the data path in accordance with the module control signals. The data path corresponding to the each data signal line includes at least one tristate buffer controlled by the command processing circuit and a delay circuit configured to delay a signal through the data path by an amount determined by the command processing circuit in response to at least one of the module control signals.

95. 发明授权

US09867283B2 Package board and prepreg 有权
公开(公告)号：US09867283B2
公开(公告)日：2018-01-09
申请号：US15197736
申请日：2016-06-29
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-gyu Kim , Hyun Lee , Dong-han Kim
IPC分类号： H05K1/03 , H05K1/02 , H01L23/498 , H01L21/48 , H05K3/00
CPC分类号： H05K1/0271 , H01L21/4846 , H01L23/145 , H01L23/49838 , H05K1/03 , H05K1/0366 , H05K3/0011 , H05K2201/0287 , H05K2201/029 , H05K2201/0293 , H05K2201/2009
摘要： A package board includes a stack structure that includes a circuit layer and a fiber layer. The fiber layer includes at least one first fiber that extends in a first direction and is a non-woven fiber. Also, a prepreg includes a first fiber that is a non-woven fiber; a plurality of second fibers that are spaced apart from the first fiber and are woven fibers; and an insulating layer that fills gaps between the first fiber and the plurality of second fibers.

96. 发明授权

US09824035B2 Memory module with timing-controlled data paths in distributed data buffers 有权
公开(公告)号：US09824035B2
公开(公告)日：2017-11-21
申请号：US15426064
申请日：2017-02-07
申请人： Netlist, Inc.
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F3/00 , G06F12/00 , G06F13/00 , G06F13/16 , G06F3/06 , G11C8/18
CPC分类号： G06F13/1673 , G06F1/10 , G06F3/0613 , G06F3/0647 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F13/1642 , G06F13/28 , G06F13/4027 , G11C5/04 , G11C7/1006 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/20 , G11C8/12 , G11C8/18 , G11C16/00 , G11C29/023 , G11C29/028 , G11C2029/0407
摘要： A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

97. 发明授权

US09606907B2 Memory module with distributed data buffers and method of operation 有权
公开(公告)号：US09606907B2
公开(公告)日：2017-03-28
申请号：US13970606
申请日：2013-08-20
申请人： Netlist, Inc.
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/00 , G11C5/02 , G11C5/04 , G11C5/06 , G11C8/12
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

98. 发明授权

US09531467B2 Opportunistic downlink interference alignment 有权
标题翻译：机会性下行干扰对齐
公开(公告)号：US09531467B2
公开(公告)日：2016-12-27
申请号：US14581430
申请日：2014-12-23
申请人： Industry-Academic Cooperation Foundation Gyeongsang National University
发明人： Bang Chul Jung , Won Yong Shin , Hyun Jong Yang , Jae Joon Park , Kwang Jae Lim , Jae Sun Cha , Eun Kyung Kim , Hyun Lee , Sung Cheol Chang
IPC分类号： H04B7/08 , H04W28/04 , H04B7/04 , H04B7/06
CPC分类号： H04B7/086 , H04B7/0413 , H04B7/0617 , H04B7/0619 , H04B7/0632 , H04W28/04
摘要： A communication system configured to send data using an interference alignment scheme is disclosed herein. The disclosed communication system includes an MS and a BS. The disclosed BS sends data using a transmission beamforming matrix that minimizes intra-cell interference. The disclosed MS receives the data using a reception beamforming matrix that minimizes inter-cell interference. The BS sends information about a reference beamforming matrix to the MS, and sends a pilot signal to the MS using the reference beamforming matrix. The MS estimates an effective channel using the reference beamforming matrix, and calculates the intensity of an interference signal from an interference BS.
摘要翻译：本文公开了配置为使用干扰对准方案发送数据的通信系统。所公开的通信系统包括MS和BS。公开的BS使用最小化小区内干扰的发送波束成形矩阵来发送数据。所公开的MS使用最小化小区间干扰的接收波束形成矩阵来接收数据。 BS向MS发送关于参考波束成形矩阵的信息，并使用参考波束形成矩阵向MS发送导频信号。 MS使用参考波束成形矩阵估计有效信道，并且计算来自干扰BS的干扰信号的强度。

99. 发明授权

US09436600B2 Non-volatile memory storage for multi-channel memory system 有权
标题翻译：用于多通道存储系统的非易失性存储器
公开(公告)号：US09436600B2
公开(公告)日：2016-09-06
申请号：US14302292
申请日：2014-06-11
申请人： Netlist, Inc.
发明人： Hyun Lee
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0653 , G06F3/0685 , G06F12/0246 , G06F12/0815 , G06F12/0868 , G06F2212/214 , G06F2212/621
摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.
摘要翻译：具有多通道易失性存储器子系统的存储器系统耦合到非易失性存储器子系统以提供独立的，可配置的数据备份。易失性存储器子系统具有使用诸如DRAM存储器的易失性存储器形式的一个或多个主存储器模块，NV子系统为其提供选择性持久备份。主内存模块是使用DDR SDRAM内存设备的双列直插式内存模块或DIMM。非易失性存储器子系统（NV备份）包括NV控制器和非易失性存储器NVM。 NV备份还可以包括一个内存缓存，以帮助处理和存储数据。在某些实施例中，NV控制器和非易失性存储器经由相关联的信号线耦合到主存储器的一个或多个DIMM通道。这样的信号线可以是例如母板上的迹线，并且可以包括用于传送数据，地址和/或控制信号的一个或多个信号总线。 NV控制器和非易失性存储器可以安装在主板上。

100. 发明申请

US20160196223A1 FLASH-DRAM HYBRID MEMORY MODULE 有权
公开(公告)号：US20160196223A1
公开(公告)日：2016-07-07
申请号：US14840865
申请日：2015-08-31
申请人： Netlist, Inc.
发明人： Hyun Lee , Chi-She Chen , Jeffrey C. Solomon , Scott H. Milton , Jayesh Bhakta
IPC分类号： G06F13/28 , G06F13/40 , G06F3/06
CPC分类号： G06F13/28 , G06F1/185 , G06F3/0613 , G06F3/0659 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F13/4027 , G06F13/4243 , G06F2212/205 , G06F2212/7208 , G11C7/1072 , G11C14/0018
摘要： A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

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