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1. 发明申请

US20230132146A1 LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCESSOR 有权
公开(公告)号：US20230132146A1
公开(公告)日：2023-04-27
申请号：US18048911
申请日：2022-10-24
申请人： TACHYUM LTD.
发明人： Radoslav DANILAK , Rodney MULLENDORE , William RADKE , Chi TO
IPC分类号： G11C5/04 , G11C11/4076 , G11C7/10 , G11C7/22 , H05K1/18
摘要： A memory stick configured for use with a processor in a computer is provided. The memory stick includes a printed circuit board with first and second sides, each of the first and second sides including eighteen memory chips, each of the memory chips being an ×8 DRAM chip; the eighteen memory chips being distributed into first, second, third and fourth rows, the first row and the second row being on a left half of the printed circuit board and the third and fourth row being on a right half of the printed circuit board; and the printed circuit board including at least 400 pins including at least 16 pins for ECC bits and at least 128 pins for data bits; wherein at least the memory chips and the 128 pins for data bits establish a 128-bit data width to communicate.

2. 发明授权

US11632112B2 Integrated circuit device with separate die for programmable fabric and programmable fabric support circuitry 有权
公开(公告)号：US11632112B2
公开(公告)日：2023-04-18
申请号：US15855419
申请日：2017-12-27
申请人： Intel Corporation
发明人： Ravi Prakash Gutala , Aravind Raghavendra Dasu , Sean R. Atsatt , Scott J. Weber
IPC分类号： G06F7/38 , H03K19/173 , H03K19/0175 , G06F3/06 , G11C11/417 , H01L25/18 , H01L27/02 , H01L23/48 , H01L23/538 , H01L23/00 , H01L25/00 , H01L23/367 , G11C7/10 , H03K19/17796 , G11C5/04 , G06F30/34
摘要： An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

3. 发明授权

US11609870B2 Off-module data buffer 有权
公开(公告)号：US11609870B2
公开(公告)日：2023-03-21
申请号：US17296532
申请日：2019-11-21
申请人： Rambus Inc.
发明人： Frederick A. Ware , Christopher Haywood
IPC分类号： G06F13/16 , G06F13/40 , G11C7/10 , G11C5/04 , G11C11/4093 , G11C11/4096
摘要： In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

4. 发明授权

US11573849B2 Memory module register access 有权
公开(公告)号：US11573849B2
公开(公告)日：2023-02-07
申请号：US17236445
申请日：2021-04-21
申请人： Rambus Inc.
发明人： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
IPC分类号： G06F11/07 , G11C29/44 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

5. 发明授权

US11567695B2 Buffer circuit with data bit inversion 有权
公开(公告)号：US11567695B2
公开(公告)日：2023-01-31
申请号：US17575524
申请日：2022-01-13
申请人： Rambus Inc.
发明人： Scott C. Best
IPC分类号： G06F3/06 , G11C7/10 , G11C5/04
摘要： A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

6. 发明授权

US11551735B2 High performance, non-volatile memory module 有权
公开(公告)号：US11551735B2
公开(公告)日：2023-01-10
申请号：US15555470
申请日：2016-03-11
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely Tsern , John Eric Linstadt
IPC分类号： G11C11/00 , G11C5/04 , G11C5/06 , G06F3/06 , G06F11/10 , G11C7/10 , G11C7/12
摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

7. 发明授权

US11538703B2 Substrate housing container 有权
公开(公告)号：US11538703B2
公开(公告)日：2022-12-27
申请号：US16483589
申请日：2017-02-06
申请人： Achilles Corporation
发明人： Masayuki Nishijima
IPC分类号： G11C15/04 , H01L21/673 , H01L21/677 , H01L21/687 , G11C5/04
摘要： A substrate housing container (1) includes (i) a container body (10) having one end that is provided with an opening (11) and another end that is provided with a mount element (12) on which substrates (W) are stacked, the mount element 12 facing the opening (11), and (ii) a cover (20) to cover the opening (11), wherein the cover (20) includes a lid portion (21) to cover the opening (11) and at least two holding members (22) disposed on the lid portion (21), the holding members (22) being configured to swing in a central direction of the lid portion (21) and to press outer sides of the substrates (W) accommodated in the container body (10) with the substrates (W) stacked, the container body (10) has guide grooves (13) to make tips (22a) of the holding members (22) move from an outer side of the mount element (12) to an inner sides of the mount element (12) to guide the tips (22a) of the holding members (22) to positions at which the holding members (22) press the outer sides of the substrates (W), and the guide grooves (13) are formed as a dent on surfaces of the mount element (12).

8. 发明申请

US20220382693A1 MEMORY MODULE HAVING OPEN-DRAIN OUTPUT FOR ERROR REPORTING AND FOR INITIALIZATION 有权
公开(公告)号：US20220382693A1
公开(公告)日：2022-12-01
申请号：US17840593
申请日：2022-06-14
申请人： Netlist, Inc.
发明人： Hyun Lee
IPC分类号： G06F13/16 , G11C5/04 , G11C7/10 , G06F9/445 , G06F13/24 , G06F3/06 , G06F11/10 , G11C29/52 , G06F12/06
摘要： According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.

9. 发明授权

US11513955B2 Memory module with local synchronization and method of operation 有权
公开(公告)号：US11513955B2
公开(公告)日：2022-11-29
申请号：US17141978
申请日：2021-01-05
申请人： NETLIST, INC.
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/0802 , G11C5/04 , G11C29/02 , G11C7/10
摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

10. 发明申请

US20220350763A1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULES 有权
公开(公告)号：US20220350763A1
公开(公告)日：2022-11-03
申请号：US17748762
申请日：2022-05-19
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely Tsern , John Eric Linstadt , Thomas J. Giovannini , Kenneth L. Wright
IPC分类号： G06F13/28 , G11C5/04 , G11C7/10 , G06F13/16
摘要： The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

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