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91. 发明授权

US09570563B2 III-V compound and Germanium compound nanowire suspension with Germanium-containing release layer 有权
标题翻译： III-V化合物和锗复合纳米线悬浮液与含锗释放层
公开(公告)号：US09570563B2
公开(公告)日：2017-02-14
申请号：US15181680
申请日：2016-06-14
申请人： International Business Machines Corporation
发明人： Guy M. Cohen , Isaac Lauer , Alexander Reznicek , Jeffrey W. Sleight
IPC分类号： H01L21/70 , H01L29/41 , H01L21/8238 , H01L29/06 , H01L27/092 , H01L29/417 , H01L29/49 , H01L29/775
CPC分类号： H01L29/413 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L29/0673 , H01L29/41758 , H01L29/4966 , H01L29/775
摘要： A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of source/drain component(s) defining a pFET (p-type field-effect transistor) region; a first suspended nanowire, at least partially suspended over the substrate layer in the nFET region and made from III-V material; and a second suspended nanowire, at least partially suspended over the substrate layer in the pFET region and made from Germanium-containing material. In some embodiments, the first suspended nanowire and the second suspended nanowire are fabricated by adding appropriate nanowire layers on top of a Germanium-containing release layer, and then removing the Germanium-containing release layers so that the nanowires are suspended.
摘要翻译：一种装置，包括：基底层; 限定nFET（n型场效应晶体管）区域的第一组源/漏分量; 限定pFET（p型场效应晶体管）区域的第二组源/漏分量; 至少部分地悬浮在nFET区域中的衬底层上并由III-V材料制成的第一悬浮的纳米线; 和第二悬浮的纳米线，其至少部分地悬浮在pFET区域中的衬底层上并由含锗材料制成。在一些实施方案中，通过在含锗释放层的顶部上加入适当的纳米线层，然后除去含锗释放层以使纳米线悬浮，制造第一悬浮的纳米线和第二悬浮的纳米线。

92. 发明申请

US20170040120A1 ELECTRONIC DEVICE COMPRISING NANOGAP ELECTRODES AND NANOPARTICLES 审中-公开
标题翻译：包含纳米电极和纳米微粒的电子器件
公开(公告)号：US20170040120A1
公开(公告)日：2017-02-09
申请号：US15305154
申请日：2015-04-22
申请人： NEXDOT , FONDS DE L'ESPCI - GEORGES CHARPAK
发明人： Emmanuel LHUILLIER , Benoit DUBERTRET
IPC分类号： H01G9/20 , H01L21/28 , H01L29/41 , H01L51/56 , H01L51/52 , H01L31/0224
CPC分类号： H01G9/205 , B82Y10/00 , H01G9/2054 , H01L21/02551 , H01L21/02568 , H01L21/02601 , H01L21/02628 , H01L21/28 , H01L29/0665 , H01L29/0673 , H01L29/22 , H01L29/413 , H01L31/022408 , H01L31/112 , H01L33/06 , H01L51/5206 , H01L51/5221 , H01L51/56 , H01S5/1067
摘要： An electronic device includes a substrate and at least two electrodes spaced by a nanogap, wherein the at least two electrodes are bridged by at least one nanoparticle and wherein the at least one nanoparticle has an overlap area with the at least two electrodes higher than 2% of the area of the at least one nanoparticle. A method of manufacturing the electronic device and the use of the electronic device in photodetector, transistor, phototransistor, optical modulator, electrical diode, photovoltaic cell or electroluminescent component are also described.
摘要翻译：一种电子器件包括衬底和至少两个由纳米隙间隔的电极，其中所述至少两个电极由至少一个纳米颗粒桥接，并且其中所述至少一个纳米颗粒具有与所述至少两个电极重叠的重叠面积高于2％的至少一种纳米颗粒的面积。还描述了制造电子装置的方法以及在光电检测器，晶体管，光电晶体管，光调制器，电二极管，光伏电池或电致发光部件中使用电子器件。

93. 发明授权

US09536965B2 Heat spreader on GaN semiconductor device 有权
标题翻译：散热器在GaN半导体器件上
公开(公告)号：US09536965B2
公开(公告)日：2017-01-03
申请号：US14922017
申请日：2015-10-23
申请人： Dynax Semiconductor, Inc.
发明人： Yi Pei , Mengjie Zhou , Naiqian Zhang
IPC分类号： H01L29/417 , H01L29/47 , H01L29/778 , H01L29/16 , H01L29/45 , H01L29/40 , H01L29/08 , H01L29/20 , H01L29/06 , H01L29/41 , H01L23/373
CPC分类号： H01L29/41758 , H01L23/373 , H01L23/3736 , H01L29/0673 , H01L29/0847 , H01L29/1606 , H01L29/20 , H01L29/2003 , H01L29/401 , H01L29/413 , H01L29/4175 , H01L29/452 , H01L29/475 , H01L29/7786 , H01L29/7787 , H01L2924/0002 , H01L2924/13064 , H01L2924/00
摘要： A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.
摘要翻译：半导体器件包括：衬底; 位于所述基板上的多层半导体层; 位于所述多层半导体层上的源，所述源包括有源区内的第一源极部分和被动区域内的第二源极部分; 漏极，位于所述多层半导体层上，所述漏极包括所述有源区内部的第一漏极部分和所述无源区域内的第二漏极区域; 位于所述多层半导体层上的栅极，所述栅极包括所述有源区内部的第一栅极部分和所述无源区域内的第二栅极部分，所述第一栅极部分是所述第一源极部分和所述第一漏极之间的叉指形式一部分; 以及布置在第一源极部分，第一漏极部分，第一栅极部分，第二源极部分，第二漏极部分和第二栅极部分中的一个或多个处的散热层。

94. 发明授权

US09536964B2 Method for forming via profile of interconnect structure of semiconductor device structure 有权
标题翻译：用于形成半导体器件结构的互连结构的通孔轮廓的方法
公开(公告)号：US09536964B2
公开(公告)日：2017-01-03
申请号：US14725002
申请日：2015-05-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Wei-Yin Shiao , Che-Cheng Chang , Tai-Shin Cheng , Wei-Ting Chen
IPC分类号： H01L29/41 , H01L29/417 , H01L29/66 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/76804 , H01L21/76805 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76877 , H01L23/485 , H01L29/4175 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.
摘要翻译：提供了一种形成半导体器件结构的方法。该方法包括在衬底上形成第一金属层，并在第一金属层上形成电介质层。该方法包括在电介质层上形成抗反射层，在抗反射层上形成硬掩模层，并在硬掩模层上形成图案化的光致抗蚀剂层。该方法包括通过执行第一蚀刻工艺和蚀刻穿过抗反射层并通过执行第二蚀刻工艺蚀刻介电层的一部分来蚀刻抗反射层的一部分。该方法包括通过执行第三蚀刻工艺来蚀刻通过介电层，以在第一金属层上形成通孔部分。通孔部分包括第一侧壁和第二侧壁，并且第一侧壁的斜面与第二侧壁的斜面不同。

95. 发明授权

US09536885B2 Hybrid FINFET/nanowire SRAM cell using selective germanium condensation 有权
标题翻译：使用选择性锗冷凝的混合FINFET /纳米线SRAM单元
公开(公告)号：US09536885B2
公开(公告)日：2017-01-03
申请号：US14672282
申请日：2015-03-30
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/11 , H01L27/12 , H01L27/092 , H01L21/84 , H01L29/06 , H01L29/41
CPC分类号： H01L27/1108 , H01L21/823807 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/0673 , H01L29/165 , H01L29/413 , H01L29/66545
摘要： A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nFET is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pFET by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer.
摘要翻译：一种包括pFET和nFET的半导体器件，其中：（i）pFET的栅极和导体沟道与掩埋氧化物层电绝缘; 和（ii）nFET的导体通道为从掩埋氧化物层向上延伸并与之相接触的翅片的形式。此外，通过添加从掩埋氧化物层的顶面延伸的翅片结构，然后将锗局部冷凝到翅片结构的下部的晶格结构中，然后蚀刻除去栅极结构的下部，从而制造pFET的方法翅片结构，使其成为悬挂在上面并与掩埋氧化物层电绝缘的载流子通道。

96. 发明授权

US09502316B2 Method and device for producing a plurality optoelectronic elements 有权
标题翻译：用于制造多个光电元件的方法和装置
公开(公告)号：US09502316B2
公开(公告)日：2016-11-22
申请号：US14398474
申请日：2013-04-24
申请人： OSRAM OLED GmbH
发明人： Simon Schicktanz , Daniel Steffen Setz
IPC分类号： H01L21/66 , H01L29/06 , H01L51/00 , H01L51/52 , H01L51/56 , H01L29/16 , H01L29/41 , H01L51/50
CPC分类号： H01L22/20 , H01L29/0665 , H01L29/1606 , H01L29/413 , H01L51/0031 , H01L51/50 , H01L51/5262 , H01L51/56 , H01L2251/5361 , H01L2251/568
摘要： A method for producing a plurality of optoelectronic components may include measuring at least one measurement parameter for a first optoelectronic component and a second optoelectronic component, and processing the first optoelectronic component and the second optoelectronic component taking account of the measured measurement parameter value of the first optoelectronic component and the measured measurement parameter value of the second optoelectronic component, such that the optoelectronic properties of the first optoelectronic component and the optoelectronic properties of the second optoelectronic component are changed in a different way toward at least one common predefined optoelectronic target property. The processing of at least one value of a measurement parameter of the optoelectronic properties of the first optoelectronic component or of the optoelectronic properties of the second optoelectronic component toward the optoelectronic target property is formed by means of a compensation element. The compensation element is formed as a film.
摘要翻译：用于制造多个光电子部件的方法可以包括测量第一光电子部件和第二光电部件的至少一个测量参数，以及考虑第一光电子部件和第二光电部件的测量测量参数值来处理第一光电子部件和第二光电部件光电子部件和测量的第二光电子部件的测量参数值，使得第一光电子部件的光电子性质和第二光电子部件的光电子性质以不同的方式朝向至少一个共同的预定义光电目标特性改变。通过补偿元件来形成第一光电子部件的光电子特性或第二光电子部件的光电子特性的测量参数的至少一个值朝向光电子目标特性的处理。补偿元件形成为膜。

97. 发明申请

US20160336411A1 RECESSED CONTACT TO SEMICONDUCTOR NANOWIRES 审中-公开
公开(公告)号：US20160336411A1
公开(公告)日：2016-11-17
申请号：US15221811
申请日：2016-07-28
申请人： SOL VOLTAICS AB
发明人： Ingvar Åberg , Martin Magnusson , Damir Asoli , Lars Ivar Samuelson , Jonas Ohlsson
IPC分类号： H01L29/41 , H01L21/02 , H01L21/311 , H01L29/06
CPC分类号： H01L29/413 , H01L21/02164 , H01L21/02205 , H01L21/02214 , H01L21/0228 , H01L21/02603 , H01L21/31116 , H01L21/32134 , H01L27/15 , H01L29/0669 , H01L29/0676 , H01L29/20 , H01L31/022466 , H01L31/035227 , H01L31/042 , H01L31/0735 , H01L31/1852 , H01L33/02 , H01L33/16 , H01L33/38 , H01L33/385 , H01L33/42 , H01L2924/0002 , Y02E10/544 , Y02P70/521 , Y10S977/932 , H01L2924/00
摘要： A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.

98. 发明授权

US09484406B1 Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications 有权
标题翻译：用于制造用于半导体应用的器件的水平栅极的纳米线的方法
公开(公告)号：US09484406B1
公开(公告)日：2016-11-01
申请号：US14874146
申请日：2015-10-02
申请人： Applied Materials, Inc.
发明人： Shiyu Sun , Naomi Yoshida , Bingxi Wood
IPC分类号： H01L29/423 , H01L29/06 , H01L21/02 , H01L29/165 , H01L29/41
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/0206 , H01L21/02126 , H01L21/0214 , H01L21/02167 , H01L21/02233 , H01L21/02236 , H01L21/02252 , H01L21/0228 , H01L21/0231 , H01L21/67207 , H01L29/165 , H01L29/401 , H01L29/413 , H01L29/41725 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.
摘要翻译：本公开提供用于形成具有期望材料的纳米线结构的方法，用于半导体芯片的水平栅极全周（hGAA）结构场效应晶体管（FET）。在一个实例中，在衬底上形成纳米线结构的方法包括将氧含气体混合物供应到处理室中的衬底上的多材料层，其中多材料层包括重复的第一层和第二层所述第一和第二层分别具有通过限定在所述多层材料层中的开口暴露的第一组和第二组侧壁，并且在所述第二层中的所述第二侧壁组上选择性地形成氧化层。

99. 发明申请

US20160276434A1 SEMICONDUCTOR DEVICE FORMED WITH NANOWIRE 有权
标题翻译：用NANOWIRE形成的半导体器件
公开(公告)号：US20160276434A1
公开(公告)日：2016-09-22
申请号：US15166271
申请日：2016-05-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chun Jen Chen , Bin-Siang Tsai , Tsai-Yu Wen , Yu Shu Lin , Chin-Sheng Yang
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L29/41
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02255 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02535 , H01L21/02587 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/76224 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L2029/7858
摘要： A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
摘要翻译：提供半导体器件。半导体器件包括衬底; 设置在衬底上的第一纳米线; 设置在衬底上的第二纳米线; 形成在第一和第二纳米线的第一端处的第一焊盘，形成在第一和第二纳米线的第二端处的第二焊盘，其中焊盘包括与纳米线不同的材料; 以及围绕第一和第二纳米线的每一个的至少一部分的栅极。

100. 发明授权

US09431478B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431478B2
公开(公告)日：2016-08-30
申请号：US14600142
申请日：2015-01-20
申请人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
发明人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/41
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/06 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/775 , H01L29/78 , H01L29/7851 , H01L29/7853 , H01L29/78696
摘要： A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
摘要翻译：一种半导体器件包括由场绝缘层限定并沿着第一方向延伸的第一多沟道有源图案，该第一多沟道有源图案包括第一部分，该第一部分具有在向上方向上进一步向上方突出的顶表面，所述场绝缘层和所述第一部分的两侧上的第二部分，所述第二部分具有连续轮廓的侧壁和在所述场绝缘层的顶表面上向上方向突出的顶表面，并且在向上方向上突出小于第一部分的顶表面的第一部分上的栅电极，在第一多通道有源图案的第一部分上并且沿着不同于第一方向的第二方向延伸的栅电极，以及在第一部分的第二部分上的第一源极/漏极区域第一多通道有源图案并接触场绝缘层。

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