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91. 发明授权

US06943610B2 Clock distribution network using feedback for skew compensation and jitter filtering 失效
标题翻译：时钟分配网络使用反馈进行偏移补偿和抖动滤波
公开(公告)号：US06943610B2
公开(公告)日：2005-09-13
申请号：US10125591
申请日：2002-04-19
申请人： Martin Saint-Laurent
发明人： Martin Saint-Laurent
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03K5/15 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/099 , G06F1/04
CPC分类号： G06F1/10 , H03K5/133 , H03K5/1506 , H03K2005/00039 , H03K2005/00065 , H03L7/07 , H03L7/0812 , H03L7/0814 , H03L7/085 , H03L7/0995
摘要： A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.
摘要翻译：用于使用数字反馈进行偏移补偿和抖动滤波的集成电路（IC）中时钟分配的时钟分配网络。在一个实施例中，多个时钟处理器节点分布在IC的各个本地时钟区域的整个时钟分配网络中。主时钟发生器通过时钟分配网络产生主时钟，用于分配给时钟处理器节点，以补偿时钟偏移并且在相应的本地时钟区域局部滤波时钟抖动。

92. 发明授权

US06943609B2 Stratum clock state machine multiplexing switching 失效
标题翻译：层时钟状态机多路复用切换
公开(公告)号：US06943609B2
公开(公告)日：2005-09-13
申请号：US10782441
申请日：2004-02-19
申请人： George Zampetti , Bob Hamilton
发明人： George Zampetti , Bob Hamilton
IPC分类号： H03L7/07 , H04J3/06 , G06F1/04
CPC分类号： H03L7/07 , H04J3/0688
摘要： A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.
摘要翻译：一种方法包括：接收一对输入时钟信号; 利用层时钟状态机来控制多路复用器; 利用多路复用器在一对输入时钟信号中的每一个之间切换主时钟的输入; 引发相位活动; 并发送输出时钟信号。

93. 发明申请

US20050195643A1 Differential and quadrature harmonic VCO and methods therefor 失效
标题翻译：差分和正交谐波VCO及其方法
公开(公告)号：US20050195643A1
公开(公告)日：2005-09-08
申请号：US11056522
申请日：2005-02-14
申请人： Kuhnert Holger
发明人： Kuhnert Holger
IPC分类号： H03L7/07 , G11C11/00
CPC分类号： H03L7/0995
摘要： A differential and quadrature harmonic voltage controlled oscillator (VCO), and a method for generating a differential and quadrature harmonic signal. The VCO may include a first oscillation unit for generating a first and a third signal, a first combining unit for combining the first and the third signal, a second oscillation unit for generating a second and a fourth signal, and a second combining unit for combining the second and the fourth signal. The phase of the second signal is determined through a phase-invert and delay using the first signal, the phase of the third signal is determined through a phase-invert and delay using the second signal, the phase of the fourth signal is determined through a phase-invert and delay using the third signal, and the phase of the first signal is determined through a phase-invert and delay using the fourth signal.
摘要翻译：差分和正交谐波压控振荡器（VCO），以及用于产生差分和正交谐波信号的方法。 VCO可以包括用于产生第一和第三信号的第一振荡单元，用于组合第一和第三信号的第一组合单元，用于产生第二和第四信号的第二振荡单元，以及用于组合的第二组合单元第二和第四信号。通过使用第一信号的相位反转和延迟来确定第二信号的相位，通过使用第二信号的相位反相和延迟来确定第三信号的相位，通过第一信号确定第四信号的相位使用第三信号进行相位反相和延迟，并且通过使用第四信号的相位反相和延迟来确定第一信号的相位。

94. 发明申请

US20050189971A1 System with dual rail regulated locked loop 有权
标题翻译：系统具有双轨调节锁定环
公开(公告)号：US20050189971A1
公开(公告)日：2005-09-01
申请号：US11114433
申请日：2005-04-26
申请人： Jade Kizer , Benedict Lau , Craig Hampel
发明人： Jade Kizer , Benedict Lau , Craig Hampel
IPC分类号： G06F1/10 , H03L7/07 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.
摘要翻译：一种具有选择电路，加法电路和相位混频器的集成电路装置。选择电路选择多个偏移值中的一个作为选择的偏移。求和电路将所选择的偏移与相位计数值相加，相位计数值指示参考时钟信号和第一多个时钟信号之一之间的相位差。相位混频器根据所选择的偏移和相位计数值的和来组合第一多个时钟信号以产生输出时钟信号。

95. 发明授权

US06925135B2 Digital-data receiver synchronization 失效
标题翻译：数字数据接收机同步
公开(公告)号：US06925135B2
公开(公告)日：2005-08-02
申请号：US10722274
申请日：2003-11-25
申请人： Stephen F. Smith , Gary W. Turner
发明人： Stephen F. Smith , Gary W. Turner
IPC分类号： H03L7/07 , H03L7/087 , H03L7/089 , H03L7/191 , H03L7/23 , H04J3/06 , H04L7/00
CPC分类号： H03L7/0891 , H03L7/07 , H03L7/087 , H03L7/191 , H03L7/23 , H04J3/0685
摘要： Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.
摘要翻译：数字数据接收机同步提供有复合相位频率检测器，互相交叉比较反馈或两者，以提供数字数据信号的鲁棒接收。单个主时钟可用于提供频率信号。优点可以包括在中等到严重噪声条件下的快速锁定时间，锁定时更大的噪声容限和抖动，以及改善对时钟不对称性的容限。

96. 发明申请

US20050134337A1 Clock signal distribution with reduced parasitic loading effects 有权
标题翻译：时钟信号分布具有减小的寄生负载效应
公开(公告)号：US20050134337A1
公开(公告)日：2005-06-23
申请号：US10744206
申请日：2003-12-22
申请人： Seong-hoon Lee , Feng Lin
发明人： Seong-hoon Lee , Feng Lin
IPC分类号： G06F1/10 , H03L7/06 , H03L7/07 , H03L7/081 , H03L7/099
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0812 , H03L7/0995
摘要： Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL) circuit locks to the lower frequency clock signal, and outputs a corresponding lower frequency clock signal for distribution over a long trace. Power consumption caused by parasitic capacitance of the trace is thereby reduced. Parasitic effects associated with clock jitter are also reduced. A frequency multiplying phase-locked loop (PLL) circuit locks to the lower frequency clock signal, and outputs at least one clock signal having a higher frequency than the lower frequency signal.
摘要翻译：提供具有减小的寄生负载效应的时钟信号分配系统。参考时钟被分频以产生较低频率的时钟信号。延迟锁定环（DLL）电路锁定到较低频率时钟信号，并输出相应的较低频率时钟信号，以在较长的轨迹上分布。因此，由于迹线的寄生电容引起的功耗降低。与时钟抖动相关的寄生效应也降低。频率倍增锁相环（PLL）电路锁定到较低频率时钟信号，并且输出具有比低频信号更高频率的至少一个时钟信号。

97. 发明授权

US06906572B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06906572B2
公开(公告)日：2005-06-14
申请号：US10792720
申请日：2004-03-05
申请人： Hiroyuki Mizuno
发明人： Hiroyuki Mizuno
IPC分类号： H01L21/822 , G06F1/10 , G11C7/22 , G11C11/40 , H01L21/82 , H01L27/04 , H03K5/00 , H03L7/06 , H03L7/07 , H03L7/18 , H03K3/00
CPC分类号： G11C7/1066 , G06F1/10 , G11C7/22 , G11C7/222 , H03L7/06 , H03L7/07 , H03L7/18
摘要： In integrated circuit (IC) devices, skew concerns between the clock pulses supplied to different latches hinder high speed operation. An IC device therefor includes a first clock processor means to generate a third clock pulse in response to first and second clock pulses with identical phase and frequency, a second clock processor means to generate a fifth clock pulse in response the third clock pulse and a fourth clock pulse with identical phase and frequency, and first and second latch groups each including a plurality of latches, in which the second clock pulse is generated via a buffer or divider from the third clock pulse, a fourth clock pulse is generated via a buffer or divider from the fifth clock pulse, and the third and fifth clock pulses are supplied to the first and second latch groups via a buffer, respectively.

98. 发明申请

US20050064892A1 Master-Slave Local Oscillator Porting Between Radio Integrated Circuits 有权
标题翻译：主从本地振荡器在无线电集成电路之间移动
公开(公告)号：US20050064892A1
公开(公告)日：2005-03-24
申请号：US10707312
申请日：2003-12-04
申请人： Mark Cavin
发明人： Mark Cavin
IPC分类号： H03L7/07 , H03L7/22 , H03L7/23 , H04B1/28 , H04M1/00
CPC分类号： H03L7/07 , H03L7/22 , H03L7/23
摘要： A technique to share a local oscillator signal between two radio frequency integrated circuits (RFICs). The local oscillator signal generated internally by one RFIC is ported to the other RFIC for use in transmit and/or receive operation. The local oscillator signal that is ported may be an RF local oscillator signal. Each RFIC may include a bi-directional port circuit that can be operated to make the RFIC a master, slave or may be totally disabled to disable the porting feature. This is particularly useful in RFICs that are used to communicate using MIMO radio algorithms which rely for optimum performance on phase and frequency coherency among a plurality of transmitters and a plurality of receivers.
摘要翻译：一种在两个射频集成电路（RFIC）之间共享本地振荡器信号的技术。由一个RFIC内部产生的本地振荡器信号被移植到另一个RFIC，用于发送和/或接收操作。被移植的本地振荡器信号可以是RF本地振荡器信号。每个RFIC可以包括双向端口电路，其可以被操作以使RFIC成为主机，从机或可以完全禁用以禁用移植特征。这在用于使用MIMO无线电算法进行通信的RFIC中特别有用，所述MIMO无线电算法依赖于多个发射机和多个接收机之间的相位和频率一致性的最佳性能。

99. 发明申请

US20050057311A1 Clock generation system 失效
标题翻译：时钟发生系统
公开(公告)号：US20050057311A1
公开(公告)日：2005-03-17
申请号：US10919634
申请日：2004-08-17
申请人： Masayu Fujiwara
发明人： Masayu Fujiwara
IPC分类号： G11B20/14 , H03L7/00 , H03L7/07 , H03L7/099 , H03L7/183 , H03L7/197 , H03L7/23
CPC分类号： H03L7/1974 , H03L7/23
摘要： A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.
摘要翻译：提供了分频参考频率时钟作为相位比较器的参考输入。具有与另一参考频率时钟相关联的频率的可控振荡器的振荡频率信号由分频因子切换型比较输入分频电路进行频率分频。所得到的分频时钟作为比较输入提供给相位比较器。比较输入分频电路的分频因子基于分频因子控制信号从一个切换到另一个，以产生相对于另一参考频率时钟具有预定频率比的振荡频率信号。因此，以足够的S / N比获得符合MPEG格式的27MHz，33.8688MHz和36.864MHz的三个参考频率时钟。

100. 发明授权

US06839391B2 Method and apparatus for a redundant clock 有权
标题翻译：冗余时钟的方法和装置
公开(公告)号：US06839391B2
公开(公告)日：2005-01-04
申请号：US10041338
申请日：2002-01-08
申请人： Peter David Novak , Angela Carol McCrory , Dale Emerson Ray , Toni Ann Long
发明人： Peter David Novak , Angela Carol McCrory , Dale Emerson Ray , Toni Ann Long
IPC分类号： G06F1/04 , H03L7/00 , H03L7/07 , H03L7/14 , H04L7/00 , H04L7/04 , H04L29/14 , H03K17/00
CPC分类号： H03L7/143 , H03L7/07
摘要： A redundant clock system and communications cards for utilizing the system, the system including a clock source for providing a reference signal for communication cards; an alternate clock source, coupled to the clock source, for providing an alternate reference signal for the communication cards; each of the communication cards including a clock generator, referenced to one of the reference signals for providing clock signals at frequencies corresponding to functions provided by each of the communications cards, and each of the communication cards arranged to couple to a surviving one of the reference signals when a failure of the other is detected.
摘要翻译：一种用于利用系统的冗余时钟系统和通信卡，该系统包括用于为通信卡提供参考信号的时钟源; 耦合到时钟源的备用时钟源，用于为通信卡提供备用参考信号; 每个通信卡包括时钟发生器，参考用于提供与由每个通信卡提供的功能相对应的频率的时钟信号之一的参考信号，并且每个通信卡被布置成耦合到参考中的幸存的一个当检测到另一个的故障时发出信号。

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