专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180196124A1 SYNTHESIZER FOR RADAR SENSING 审中-公开
公开(公告)号：US20180196124A1
公开(公告)日：2018-07-12
申请号：US15703817
申请日：2017-09-13
申请人： Honeywell International Inc.
发明人： David C. Vacanti , Marc M. Pos
IPC分类号： G01S7/41 , G01S13/93 , G01S7/35 , G01S7/292
CPC分类号： G01S7/41 , G01S7/032 , G01S7/282 , G01S7/292 , G01S7/35 , G01S7/354 , G01S13/91 , G01S13/93 , H03L7/0991 , H03L7/22
摘要： In some examples, a radar system includes first direct digital synthesizer (DDS) circuitry and first phase-locked loop (PLL) circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry. In some examples, the radar system further includes transmitter circuitry configured to generate a radar signal based on the first sinusoidal signal. In some examples, the radar system also includes one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal. In some examples, the radar system includes second DDS circuitry, second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, and receiver circuitry configured to process the return signal based on the second sinusoidal signal.

2. 发明申请

US20180083763A1 CLOCK SYNCHRONIZATION 审中-公开
公开(公告)号：US20180083763A1
公开(公告)日：2018-03-22
申请号：US15273015
申请日：2016-09-22
申请人： QUALCOMM Incorporated
发明人： Justin Black , Cheng-Han Wang , Jeongsik Yang
IPC分类号： H04L7/00 , H03L7/00 , H03K19/21
CPC分类号： H04L7/0008 , H03K19/21 , H03L7/00 , H03L7/0812 , H03L7/143 , H03L7/22 , H04W52/02
摘要： An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

3. 发明申请

US20170187355A1 Reactance shift detection in a wireless power transmitter 审中-公开
公开(公告)号：US20170187355A1
公开(公告)日：2017-06-29
申请号：US14757914
申请日：2015-12-24
申请人： Intel Corporation
发明人： Songnan Yang , Bin Xiao , Jian Chen , Sreenivas Kasturi , Jordan E. Maslov
IPC分类号： H03J7/04 , H03H7/40 , H02J7/02
CPC分类号： H03J7/04 , H02J7/025 , H02J50/12 , H03F1/565 , H03F3/2176 , H03F3/245 , H03F2200/387 , H03F2200/435 , H03H7/40 , H03L7/1972 , H03L7/22 , H03L2207/50
摘要： Techniques for tuning in a wireless power transmitter in a system, method, and apparatus are described herein. An example of a wireless power transmitter may include a transmitter coil configured to generate a magnetic field for wirelessly charging a battery, and a tuning circuit coupled to the transmitter coil configured to retune the transmitter coil in response to a reactance shift of the transmitter coil. The wireless power transmitter may also include a tuning control circuit to detect the reactance shift and control the tuning circuit to retune the transmitter coil. The tuning control circuit is to detect the reactance by measuring a drain voltage of a power amplifier.

4. 发明授权

US09634677B2 Clock generator and integrated circuit using the same and injection-locked phase-locked loop control method 有权
公开(公告)号：US09634677B2
公开(公告)日：2017-04-25
申请号：US15052183
申请日：2016-02-24
申请人： MediaTek Inc.
发明人： Yi-Chieh Huang
IPC分类号： H03L7/06 , H03L7/099
CPC分类号： H03L7/24 , H03L7/22
摘要： A control technique for an injection-locked phase-locked loop (ILPLL) includes the following steps: providing the ILPLL with a sampling clock and an injection clock for an integral path and a proportional path of the ILPLL, respectively; making a change in the power level of the injection clock to get the phase error of the integral path of the ILPLL; and controlling the phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the ILPLL.

5. 发明授权

US09571109B2 Voltage controlled oscillator runaway prevention 有权
标题翻译：电压控制振荡器防范
公开(公告)号：US09571109B2
公开(公告)日：2017-02-14
申请号：US14671259
申请日：2015-03-27
申请人： International Business Machines Corporation
发明人： David M. Friend , James D. Strom , Alan P. Wagstaff
IPC分类号： H03L7/06 , H03L7/085 , H03L7/099 , H03L3/00 , H03B5/06 , H03L7/18 , H03L7/22 , H03L7/14 , H03L7/10
CPC分类号： H03L7/085 , H03B5/06 , H03K23/42 , H03L3/00 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L7/22 , H03L7/23
摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.
摘要翻译：用于防止锁相环（PLL）电路中的压控振荡器（VCO）失控的反馈模块可以包括第一，第二和第三输入端，以从PLL电路接收第一输出信号，参考信号和第一控制信号。反馈模块还可以包括用于产生第二控制信号的反馈电路，第二控制信号耦合到PLL电路的输入端，其中反馈电路通过比较第一输出信号的周期数来产生第二控制信号到第一阈值，以及参考信号的周期数到第二阈值。

6. 发明授权

US09548751B2 RF circuit 有权
标题翻译：射频电路
公开(公告)号：US09548751B2
公开(公告)日：2017-01-17
申请号：US14821481
申请日：2015-08-07
申请人： NXP B.V.
发明人： Jean-Robert Tourret
IPC分类号： H03L7/23 , H03L7/07 , H03L7/099 , H03L7/22 , H03L7/18 , H05B6/00
CPC分类号： H03L7/235 , H03L7/07 , H03L7/099 , H03L7/18 , H03L7/22 , H03L7/23 , H05B6/00
摘要： An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.
摘要翻译：一种用于提供相位相干信号的RF电路，包括RF电路的RF加热装置和用于在RF电路中提供相位相干信号的方法。 RF电路具有包括N分相锁相环的第一频率合成器和包括整数N个锁相环的第二频率合成器。第一频率合成器的输出经由用于将来自第一频率合成器的同步信号分配给第二频率合成器的同步信号分频器连接到第二频率合成器的整数N锁相环的相位频率检测器。第二频率合成器的整数N锁相环包括与同步信号分频器相同模数的分频器。

7. 发明申请

US20160299870A1 PLL SYSTEM WITH MASTER AND SLAVE DEVICES 有权
标题翻译：具有主和从设备的PLL系统
公开(公告)号：US20160299870A1
公开(公告)日：2016-10-13
申请号：US15090637
申请日：2016-04-05
申请人： Microsemi Semiconductor ULC
发明人： Krste Mitric , Slobodan Milijevic , Wenbao Wang , Gabriel Rusaneanu
IPC分类号： G06F13/42 , G06F1/08 , G06F13/364
CPC分类号： G06F13/4291 , G06F1/08 , G06F13/364 , H03L7/099 , H03L7/16 , H03L7/22 , H03L2207/06 , H03L2207/50
摘要： A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).
摘要翻译：主锁相环装置可与一个或多个从装置（包括从属数字控制振荡器（sDCO））相关联地操作，一个或多个数字PLL（DPLL）信道包括主数字控制振荡器（mDCO）。主同步定时器产生主定时脉冲以从mDCO读取相位和频率信息。外围接口将读取的频率和相位信息发送到一个或多个从设备。同步接口发送主定时脉冲以同步sDCO中的复制同步定时器，该复制同步定时器产生用于更新在从设备处接收的相位和频率信息的从定时脉冲。

8. 发明申请

US20150227185A1 DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING 有权
标题翻译：动态时钟和低电平切换低电平切换
公开(公告)号：US20150227185A1
公开(公告)日：2015-08-13
申请号：US14177073
申请日：2014-02-10
申请人： QUALCOMM Incorporated
发明人： Dipti Ranjan Pal , Paul Ivan Penzes , Mohamed Waleed Allam
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3296 , H03L7/22 , Y02D10/126 , Y02D10/152
摘要： Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.
摘要翻译：用于动态时钟和电压缩放的系统和方法可以在低电平时间的频率 - 电压模式之间切换集成电路。这些系统包括能够控制功率管理集成电路（PMIC），锁相环（PLL）和时钟分频器的资源功率管理器。资源功率管理器控制频率 - 电压模式之间的转换。系统和方法提供动态时钟和电压缩放，其中频率 - 电压模式之间的转换是原子操作。此外，资源功率管理器可以并行地控制许多模块，例如时钟分频器。由于频率 - 电压模式之间的较低延迟，本发明可以提供改进的系统性能并降低系统功率。

9. 发明授权

US09065458B2 Frequency synthesis and noise reduction 有权
标题翻译：频率合成和降噪
公开(公告)号：US09065458B2
公开(公告)日：2015-06-23
申请号：US13641333
申请日：2011-04-11
申请人： Robert John Mark Longstone , Ian Morrison Graham
发明人： Robert John Mark Longstone , Ian Morrison Graham
IPC分类号： H03B21/00 , H03L7/22 , H03B19/00 , H03B21/02 , H03B21/04 , H03B21/01
CPC分类号： H03L7/22 , H03B19/00 , H03B21/00 , H03B21/01 , H03B21/02 , H03B21/025 , H03B21/04
摘要： A frequency synthesizer and oscillator are disclosed for reducing noise in processed signals. The synthesizer and oscillator comprise an array of frequency dividers adapted to receive an input signal, which is derived from a single signal source having a prescribed frequency. The synthesizer and oscillator further comprise at least one frequency multiplier coupled to at least one of the frequency dividers, such that in use, the dividers and the at least one multiplier are operable to generate a plurality of frequencies which are coherent with the prescribed frequency. A regulated power supply is also disclosed comprising a filter and first and second regulators, for reducing noise in the output voltage of the power supply.
摘要翻译：公开了一种用于降低处理信号中的噪声的频率合成器和振荡器。合成器和振荡器包括适于接收从具有规定频率的单个信号源导出的输入信号的分频器阵列。合成器和振荡器还包括耦合到至少一个分频器的至少一个频率乘法器，使得在使用中，分频器和至少一个乘法器可操作以产生与规定频率相干的多个频率。还公开了一种稳压电源，其包括滤波器和第一和第二调节器，用于降低电源的输出电压中的噪声。

10. 发明授权

US09054713B2 Semiconductor device generating internal clock signal having higher frequency than that of input clock signal 有权
标题翻译：产生具有比输入时钟信号频率高的内部时钟信号的半导体器件
公开(公告)号：US09054713B2
公开(公告)日：2015-06-09
申请号：US13959119
申请日：2013-08-05
申请人： ELPIDA MEMORY, INC.
发明人： Katsuhiro Kitagawa , Hiroki Takahashi
IPC分类号： H03L7/00 , H03L7/08 , H03L7/081 , H03L7/22 , G11C7/22 , G11C11/4076 , G11C29/12 , G11C29/14
CPC分类号： H03L7/0802 , G11C7/222 , G11C11/4076 , G11C29/12015 , G11C29/14 , H03L7/0816 , H03L7/22
摘要： Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.
摘要翻译：这里公开了一种装置，其包括：多个延迟电路，每个延迟电路包括输入节点，输出节点，第一功率节点和第二功率节点，以及控制电路。延迟电路与接收第一时钟信号的前导延迟电路的输入节点和最后一个延迟电路的输出节点串联耦合，产生第二时钟信号。控制电路被耦合以接收第一和第二时钟信号，以控制在第一和第二电力线之间提供的工作电压。延迟电路的第一功率节点共同连接到第一电力线，并且第二电力节点延迟电路共同连接到第二电力线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式