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91. 发明授权

US11374169B2 Magnetic random access memory 有权
公开(公告)号：US11374169B2
公开(公告)日：2022-06-28
申请号：US16939613
申请日：2020-07-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Baohua Niu , Ji-Feng Ying
IPC分类号： H01L43/10 , G11C11/16 , H01L43/08 , H01L43/12 , H01L27/22 , H01L21/62
摘要： A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.

92. 发明授权

US11367496B2 Memory circuit 有权
公开(公告)号：US11367496B2
公开(公告)日：2022-06-21
申请号：US17250417
申请日：2019-07-25
申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION
发明人： Hiroyuki Tezuka , Masami Kuroda
IPC分类号： G11C29/24 , G11C11/16 , G11C13/00 , G11C29/02
摘要： The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.

93. 发明授权

US11366949B2 Memory cell layout for low current field-induced MRAM 有权
公开(公告)号：US11366949B2
公开(公告)日：2022-06-21
申请号：US16834016
申请日：2020-03-30
申请人： III HOLDINGS 1, LLC
发明人： Krishnakumar Mani
IPC分类号： G06F30/39 , H01L27/22 , G11C11/16
摘要： Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

94. 发明申请

US20220188618A1 NEUROMORPHIC DEVICE 有权
公开(公告)号：US20220188618A1
公开(公告)日：2022-06-16
申请号：US17507561
申请日：2021-10-21
申请人： TDK CORPORATION
发明人： Shogo YAMADA , Tatsuo SHIBATA
IPC分类号： G06N3/063 , H01L27/22 , H01L43/02 , G11C11/16 , G11C11/54
摘要： This neuromorphic device including: a first element group; and a second element group, in which each of the first element group and the second element group includes a plurality of magnetic domain wall movement elements, each of the plurality of magnetic domain wall movement elements includes a magnetic domain wall movement layer, a ferromagnetic layer, and a non-magnetic layer interposed between the magnetic domain wall movement layer and the ferromagnetic layer, a length of the magnetic domain wall movement layer of each of the magnetic domain wall movement elements belonging to the first element group in a longitudinal direction is shorter than a length of the magnetic domain wall movement layer of each of the magnetic domain wall movement elements belonging to the second element group in the longitudinal direction, and a resistance changing rate when a predetermined pulse is input is higher for each of the magnetic domain wall movement elements belonging to the first element group than for each of the magnetic domain wall movement elements belonging to the second element group.

95. 发明授权

US11354098B2 Configurable non-volatile arithmetic memory operators 有权
公开(公告)号：US11354098B2
公开(公告)日：2022-06-07
申请号：US16516620
申请日：2019-07-19
申请人： SYNERGER INC.
发明人： Lee Wang
IPC分类号： G06F7/523 , H03K19/20 , H03K19/21 , G06F7/502 , G11C13/00 , G11C11/16
摘要： The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

96. 发明申请

US20220173307A1 Topological Insulator/Normal Metal Bilayers as Spin Hall Materials for Spin Orbit Torque Devices, and Methods of Fabrication of Same 有权
公开(公告)号：US20220173307A1
公开(公告)日：2022-06-02
申请号：US17457348
申请日：2021-12-02
申请人： Northeastern University
发明人： Nian-Xiang Sun , Nirjhar Bhattacharjee
IPC分类号： H01L43/06 , G11C11/16 , H01L43/04 , H01L43/14 , H01L27/22 , H01L43/10
摘要： A thin film heterostructure of a topological insulator (TI) with a normal metal (NM) is used as a highly energy efficient and low power dissipation spin Hall Material (SHM). The TI material is sputter deposited onto a substrate and cooled in high vacuum, and an NM material is sputter deposited onto the TI film. The structure and method is compatible with complementary metal oxide (CMOS) processes, and with growth of large-area TI films for wafer-level device fabrication.

97. 发明授权

US11348629B2 Giant spin hall-based compact neuromorphic cell optimized for differential read inference 有权
公开(公告)号：US11348629B2
公开(公告)日：2022-05-31
申请号：US17000009
申请日：2020-08-21
申请人： Samsung Electronics Co., Ltd.
发明人： Titash Rakshit , Ryan Hatcher , Jorge A. Kittl
IPC分类号： G11C11/16 , H01L43/06 , H01L43/04 , G06N3/063 , G06F7/50 , H01L43/10 , H01L43/08
摘要： A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

98. 发明授权

US11348628B2 Non-volatle memory with virtual ground voltage provided to unselected column lines during memory read operation 有权
公开(公告)号：US11348628B2
公开(公告)日：2022-05-31
申请号：US17032516
申请日：2020-09-25
申请人： NXP USA, Inc.
发明人： Karthik Ramanan , Jon Scott Choy
IPC分类号： G11C11/16 , G11C13/00
摘要： A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.

99. 发明授权

US11348627B2 Race-track memory with improved domain wall motion control 有权
公开(公告)号：US11348627B2
公开(公告)日：2022-05-31
申请号：US17127732
申请日：2020-12-18
申请人： Samsung Electronics Co., Ltd.
发明人： Dmytro Apalkov , Sungchul Lee , Roman Chepulskyy
IPC分类号： G11C11/00 , G11C11/16 , G11C11/18
摘要： A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.

100. 发明申请

US20220165936A1 STRUCTURE AND METHOD FOR MRAM DEVICES HAVING SPACER ELEMENT 有权
公开(公告)号：US20220165936A1
公开(公告)日：2022-05-26
申请号：US17247058
申请日：2020-11-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsiang-Ku SHEN , Dian-Hau CHEN
IPC分类号： H01L43/08 , H01L43/10 , H01L43/02 , H01L43/12 , H01L27/22 , G11C11/16 , H01F10/32
摘要： Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.

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