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1. 发明申请

US20220374204A1 HALF-ADDER, FULL-ADDER AND MULTIPLIER BASED ON MEMRISTOR ARRAY 有权
公开(公告)号：US20220374204A1
公开(公告)日：2022-11-24
申请号：US17771826
申请日：2019-12-09
申请人： ZHUHAI FUDAN INNOVATION INSTITUTE
发明人： Liang Zou
IPC分类号： G06F7/544 , G06F7/502
摘要： The present invention discloses a memristor array, comprising metal wires and memristors; the metal wires are arranged laterally and vertically; a memristor is arranged at the intersection of every two metal wires; the connection/disconnection of the metal wires is judged according to the resistance values of the memristors; and an adder is constituted according to the resistance value states of the memristors. The present invention provides a memristor-CMOS hybrid multiplication core circuit, in which one input of multiplication can be stored in a memristor network, one part of operation is completed in a memory network, the other part of operation is completed through a CMOS circuit, thereby reducing frequent data calls by half, and the power consumption of the CMOS circuit is further reduced by reducing competitive adventure in the operation process, thereby greatly reducing the overall energy consumption.

2. 发明授权

US10223071B2 Energy-efficient variable power adder and methods of use thereof 有权
公开(公告)号：US10223071B2
公开(公告)日：2019-03-05
申请号：US15488019
申请日：2017-04-14
申请人： QUALCOMM Incorporated
发明人： Hari Rao
IPC分类号： G06F7/502 , G06F7/505 , G06F7/506
摘要： A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

3. 发明授权

US3189735A Parallel coded digit adder 失效
标题翻译：并行编码数字加法器
公开(公告)号：US3189735A
公开(公告)日：1965-06-15
申请号：US10073561
申请日：1961-04-04
申请人： NCR CO
发明人： GUNDERSON ROBERT O , TANG TOM T
IPC分类号： G06F7/50 , G06F7/502
CPC分类号： G06F7/502 , G06F7/494 , G06F7/50 , G06F2207/4924

4. 发明授权

US3001711A Transistor adder circuitry 失效
标题翻译：晶体管加法器电路
公开(公告)号：US3001711A
公开(公告)日：1961-09-26
申请号：US62584756
申请日：1956-12-03
申请人： NCR CO
发明人： ROBERT FROHMAN
IPC分类号： G06F7/50 , G06F7/502 , H03K19/21
CPC分类号： G06F7/502 , H03K19/212

5. 发明公开

US20240184526A1 MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20240184526A1
公开(公告)日：2024-06-06
申请号：US18329045
申请日：2023-06-05
申请人： Samsung Electronics Co., Ltd.
发明人： Seungwoo SEO , Sanghoon CHA
IPC分类号： G06F7/544 , G06F7/502 , G06F9/30
CPC分类号： G06F7/5443 , G06F7/502 , G06F9/30145
摘要： A memory device includes: a plurality of memory banks divided by a plurality of channels comprising a first channel and a second channel; and a channel-level processing element (PE) configured to generate an in-memory computation result by performing an operation using a first partial result generated based on data stored in a memory bank of the first channel among the plurality of memory banks and a second partial result generated based on data stored in a memory bank of the second channel among the plurality of memory banks.

6. 发明申请

US20220365751A1 COMPRESSED WALLACE TREES IN FMA CIRCUITS 有权
公开(公告)号：US20220365751A1
公开(公告)日：2022-11-17
申请号：US17358722
申请日：2021-06-25
申请人： Intel Corporation
发明人： Aditya Varma , Mahesh Kumashikar , Michael Espig
IPC分类号： G06F7/53 , G06F7/502 , G06F15/80
摘要： An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.

7. 发明授权

US11294632B2 Multiplication accumulating device and method thereof 有权
公开(公告)号：US11294632B2
公开(公告)日：2022-04-05
申请号：US16861234
申请日：2020-04-29
申请人： Chung Yuan Christian University
发明人： Shih-Hsu Huang , Che-Wei Tung
IPC分类号： G06F7/523 , G06F9/30 , G06F7/502
摘要： A multiplication accumulating device and a method thereof are provided. The multiplication accumulating device includes a product generator, a plurality of registers, a product reducer, and an adder. The product generator performs a product operation on a multiplicand and a multiplier to generate a product result of 2N−1 columns. The product reducer is used to append data from a portion of the plurality of registers to the columns in the product result to generate an appending result of 2N−1 columns. The product reducer performs a reduction operation on the appending result according to a column height of each column in the appending result to obtain a reduced result. The product reducer renews the data in the plurality of registers according to the reduced result. The adder adds the data in the plurality of registers according to an accumulation signal to generate a multiplication accumulating operation result.

8. 发明授权

US5068815A Optical full adder 失效
标题翻译：光学全面添加
公开(公告)号：US5068815A
公开(公告)日：1991-11-26
申请号：US541309
申请日：1990-06-21
申请人： Yoshihiko Mizushima , Kazutoshi Nakajima , Toru Hirohata , Takashi Iida , Yoshihisa Warashina , Kenichi Sugimoto , Tomoko Suzuki , Hirofumi Kan
发明人： Yoshihiko Mizushima , Kazutoshi Nakajima , Toru Hirohata , Takashi Iida , Yoshihisa Warashina , Kenichi Sugimoto , Tomoko Suzuki , Hirofumi Kan
IPC分类号： G02F3/00 , G06E1/04 , G06F7/50 , G06F7/502
CPC分类号： G06F7/502 , G06E1/04
摘要： SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier. The optical latch memory is an optical flip-flop memory in which a high-speed light-receiving element produces an electric signal in response to an input optical signals, and a high-speed light-emitting element produces, in response to the electric signal guided from the light-receiving element, feed-back light to be applied to the light-receiving element and an output optical signal.

9. 发明授权

US4907184A Arithmetic operation circuit 失效
标题翻译：算术运算电路
公开(公告)号：US4907184A
公开(公告)日：1990-03-06
申请号：US132368
申请日：1987-12-14
申请人： Tetsuo Nakano , Masahiro Iwamura , Kozaburo Kurita
发明人： Tetsuo Nakano , Masahiro Iwamura , Kozaburo Kurita
IPC分类号： H03K19/01 , G06F7/50 , G06F7/502 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/092
CPC分类号： G06F7/502
摘要： An arithmetic operation circuit is provided which includes a logic processing circuit having a first metal-oxide-semiconductor-field-effect-transistor (MOSFET) column cascade-connecting a plurality of MOSFETs and a second MOSFET column cascade-connecting a plurality of MOSFETs. First and second ends of the second MOSFET column are respectively connected to first and second ends of said first column. A first power supply voltage is coupled to the common connecting point of the first ends of said first and second MOSFET columns. An amplifying circuit, including the grounded emitter type bipolar transistor, is provided such that the base thereof is connected to the common connecting point of the second ends of said first and second MOSFET columns.
摘要翻译：提供了一种算术运算电路，其包括具有级联连接多个MOSFET的第一金属氧化物半导体场效应晶体管（MOSFET）列和串联连接多个MOSFET的第二MOSFET列的逻辑处理电路。第二MOSFET列的第一和第二端分别连接到所述第一列的第一和第二端。第一电源电压耦合到所述第一和第二MOSFET列的第一端的公共连接点。包括接地的发射极型双极晶体管的放大电路被设置成使得其基极连接到所述第一和第二MOSFET列的第二端的公共连接点。

10. 发明授权

US4739503A Carry/borrow propagate adder/subtractor 失效
标题翻译：携带/借位传播加法器/减法器
公开(公告)号：US4739503A
公开(公告)日：1988-04-19
申请号：US853854
申请日：1986-04-21
申请人： John Armer , Erwin J. Wittmann
发明人： John Armer , Erwin J. Wittmann
IPC分类号： G06F7/50 , G06F7/502
CPC分类号： G06F7/502 , G06F2207/3876
摘要： A digital arithmetic combiner having improved overflow signal propagation delay characteristics is disclosed. Such an arithmetic combiner includes a tristate device having a data input terminal coupled to an overflow input terminal and a data terminal coupled to an overflow output terminal. A tristate control terminal is coupled to the output of logic circuitry. The logic circuitry is responsive to operand input signals and enables the tristate device to generate a signal at its data output terminal when the operand input signals have different logic states. In addition, an overflow generator is responsive to the operand input signals, and generates a signal indicating overflow conditions at the overflow output terminal when the operand input signals have the same logic state.
摘要翻译：公开了具有改进的溢出信号传播延迟特性的数字运算组合器。这种算术组合器包括具有耦合到溢出输入端的数据输入端和耦合到溢出输出端的数据端的三态装置。三态控制端子耦合到逻辑电路的输出端。当操作数输入信号具有不同的逻辑状态时，逻辑电路响应于操作数输入信号，并使得三态装置在其数据输出端产生信号。此外，当操作数输入信号具有相同的逻辑状态时，溢出发生器响应于操作数输入信号，并且产生指示溢出输出端的溢出条件的信号。

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