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91. 发明授权

US09330935B2 Plasma etching method and plasma etching apparatus 有权
标题翻译：等离子体蚀刻方法和等离子体蚀刻装置
公开(公告)号：US09330935B2
公开(公告)日：2016-05-03
申请号：US14074020
申请日：2013-11-07
申请人： TOKYO ELECTRON LIMITED
发明人： Toru Hisamatsu , Masanobu Honda , Yoshihide Kihara
IPC分类号： H01L21/32 , H01L21/311 , H01L21/027
CPC分类号： H01L21/31138 , H01J2237/334 , H01L21/0273 , H01L21/31144
摘要： Disclosed is a plasma etching method which suppresses the narrowing of the line-width of the line formed by etching and maintain the height of a remaining photoresist. The plasma etching method includes a modification process and an etching process. The modification process modifies a photoresist having a predetermined pattern by plasma of HBr/Ar gas while applying a negative DC voltage to an upper electrode containing silicon disposed to face a target object in which an organic film and the photoresist are sequentially laminated. The etching process etches the organic film by plasma of a processing gas which contains a CF-based gas and a CHF-based gas.
摘要翻译：公开了一种等离子体蚀刻方法，其抑制由蚀刻形成的线的线宽变窄并保持剩余的光致抗蚀剂的高度。等离子体蚀刻方法包括修改处理和蚀刻处理。修改方法通过HBr / Ar气体的等离子体修饰具有预定图案的光致抗蚀剂，同时向包含硅的上部电极施加负的DC电压，所述上部电极被设置为面向其中依次层叠有机膜和光致抗蚀剂的目标物体。蚀刻工艺通过含有CF基气体和基于CHF的气体的处理气体的等离子体来蚀刻有机膜。

92. 发明授权

US09274259B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US09274259B2
公开(公告)日：2016-03-01
申请号：US13689483
申请日：2012-11-29
申请人： LG Display Co., Ltd.
发明人： Ii Jeon , Su Jung Park
IPC分类号： G02B5/30 , H01L27/32 , H01L21/32 , H01L51/52
CPC分类号： G02B5/30 , G02B5/3033 , G02B5/3083 , H01L21/32 , H01L27/32 , H01L51/5281
摘要： Embodiments relate to a display device for enhancing image quality. The disclosed display device includes: a display panel configured to display an image; a Poly-Vinyl Acetate (PVA) layer configured to linearly polarize external light; and a Quarter Wave Plate (QWP) configured to circularly polarize light where the QWP has an in-plane retardation value of below 140 nm.
摘要翻译：实施例涉及用于增强图像质量的显示装置。所公开的显示装置包括：显示面板，被配置为显示图像; 配置成线性偏振外部光的聚乙酸乙烯酯（PVA）层; 以及四分之一波片（QWP），其被配置为使QWP的面内延迟值低于140nm的光圆偏振。

93. 发明申请

US20160056233A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160056233A1
公开(公告)日：2016-02-25
申请号：US14818516
申请日：2015-08-05
申请人： Renesas Electronics Corporation
发明人： Akira MITSUIKI , Tomoo NAKAYAMA , Shigeaki SHIMIZU , Hiroyuki OKUAKI
IPC分类号： H01L29/06 , H01L27/088 , H01L21/311 , H01L29/78 , H01L21/762 , H01L21/32
CPC分类号： H01L27/088 , H01L21/3083 , H01L21/31111 , H01L21/31144 , H01L21/32 , H01L21/76232 , H01L21/823418 , H01L21/823456 , H01L29/0649 , H01L29/0653 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/78 , H01L29/7833 , H01L29/7835
摘要： Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
摘要翻译：抑制了凹部附近的电场集中。栅极绝缘膜设置在其上具有漏极区域和第一凹部的衬底上。第一凹部位于栅极绝缘膜和漏极区之间，并且填充有绝缘膜。绝缘膜在靠近栅极绝缘膜的一侧具有第二凹部。由第一凹部的内侧面和基板的表面限定的角度在靠近栅极绝缘膜的漏极区域的一侧为圆形。

94. 发明授权

US09269793B2 Method and system for a gallium nitride self-aligned vertical MESFET 有权
标题翻译：氮化镓自对准垂直MESFET的方法和系统
公开(公告)号：US09269793B2
公开(公告)日：2016-02-23
申请号：US14489761
申请日：2014-09-18
申请人： Avogy, Inc.
发明人： Richard J. Brown , Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , David P. Bour
IPC分类号： H01L29/20 , H01L21/20 , H01L21/332 , H01L29/66 , H01L29/812 , H01L29/808 , H01L21/02 , H01L21/32 , H01L29/36 , H01L29/47 , H01L29/10 , H01L29/16
CPC分类号： H01L29/66856 , H01L21/0254 , H01L21/02647 , H01L21/32 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/475 , H01L29/8083 , H01L29/812 , H01L29/8122
摘要： A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.
摘要翻译：半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。半导体衬底还包括耦合到漂移区的沟道区。通道区域由基本沿着生长方向设置的通道侧壁限定。半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

95. 发明授权

US09250534B2 Nonaqueous cleaning liquid and method for etching processing of silicon substrate 有权
标题翻译：非水性清洗液及硅衬底蚀刻处理方法
公开(公告)号：US09250534B2
公开(公告)日：2016-02-02
申请号：US13939549
申请日：2013-07-11
申请人： Tokyo Ohka Kogyo Co., Ltd.
发明人： Daijiro Mori , Takayuki Haraguchi
IPC分类号： G03F7/42 , H01L21/32 , H01L21/306 , H01L21/321 , H01L21/02 , H01L21/3065 , H01L21/311 , C11D7/06 , C11D7/28 , C11D7/32 , C11D7/50 , C11D11/00 , H01L21/768 , B81C1/00 , C11D7/26 , C11D7/34
CPC分类号： G03F7/426 , B81C1/00849 , C11D7/06 , C11D7/261 , C11D7/28 , C11D7/3209 , C11D7/3281 , C11D7/34 , C11D7/5022 , C11D11/0047 , G03F7/425 , H01L21/02057 , H01L21/30604 , H01L21/30655 , H01L21/31133 , H01L21/3212 , H01L21/76898
摘要： A nonaqueous cleaning liquid comprising a fluoroalkanol, a quaternary ammonium hydroxide, and an organic solvent. Compounds represented by formulae (1) and (2). Fluoroalkanol compounds include (1) H(CF2)aCH2—OH and (2) F(CF2)b(CH2)c—OH In which a and b are each an integer of from 2 to 6, and c is an integer of 1 or 2.
摘要翻译：包含氟烷醇，季铵氢氧化物和有机溶剂的非水性清洗液。由式（1）和（2）表示的化合物。氟烷醇化合物包括（1）H（CF 2）a CH 2 -OH和（2）F（CF 2）b（CH 2）c -OH其中a和b各自为2至6的整数，c为整数1 或2。

96. 发明申请

US20150357203A1 PATTERNING METHOD AND PATTERNING APPARATUS 审中-公开
标题翻译：绘图方法和绘图装置
公开(公告)号：US20150357203A1
公开(公告)日：2015-12-10
申请号：US14296862
申请日：2014-06-05
申请人： MACRONIX International Co., Ltd.
发明人： Ta-Hone Yang
IPC分类号： H01L21/32 , H01L27/115 , H01L21/266 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/3065 , H01J37/32899
摘要： A patterning method is described. A patterned mask layer is formed on a material layer, having therein a first opening exposing a portion of the material layer. A pre-treatment process is performed to modify the material layer exposed in the first opening and form a modified region therein. An etching process is performed to remove the material layer in the modified region at least and form a second opening in the material layer.
摘要翻译：描述图案化方法。图案化的掩模层形成在材料层上，其中具有暴露材料层的一部分的第一开口。执行预处理工艺以改变在第一开口中暴露的材料层，并在其中形成改性区域。进行蚀刻处理，以至少在材料层中除去改性区域中的材料层并形成第二开口。

97. 发明申请

US20150162356A1 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20150162356A1
公开(公告)日：2015-06-11
申请号：US14316523
申请日：2014-06-26
申请人： Samsung Display Co., Ltd.
发明人： Seung-Bo Shim , Dong-Hyun Yu , Jin-Ho Ju
IPC分类号： H01L27/12 , H01L21/32
CPC分类号： G03F1/50 , G03F1/00 , H01L21/0274 , H01L21/31144 , H01L21/32 , H01L27/1214 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L29/66757 , H01L51/0541 , H01L51/0545
摘要： A display device includes a substrate including a first region and a second region, a gate line and a data line on the substrate, a thin film transistor on the substrate, being connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, wherein the second region has a second contact hole of which an area is larger than that of a first contact hole of the first region.
摘要翻译：一种显示装置，包括：基板，包括第一区域和第二区域;基板上的栅极线和数据线;基板上的薄膜晶体管，连接到栅极线和数据线;以及连接有像素电极的像素电极到所述薄膜晶体管，其中所述第二区域具有第二接触孔，所述第二接触孔的面积大于所述第一区域的第一接触孔的面积。

98. 发明申请

US20150140825A1 Method for Chemical Polishing and Planarization 有权
标题翻译：化学抛光和平面化方法
公开(公告)号：US20150140825A1
公开(公告)日：2015-05-21
申请号：US14532717
申请日：2014-11-04
申请人： Tokyo Electron Limited
发明人： Anton J. deVilliers
IPC分类号： H01L21/3105 , H01L21/306 , H01L21/321 , H01L21/027 , H01L21/32
CPC分类号： H01L21/31056 , G03F7/094 , H01L21/0276 , H01L21/30604 , H01L21/31058 , H01L21/32 , H01L21/32115
摘要： A chemical planarization process described herein can be used for planarizing a substrate without using mechanical abrasion. A developable planarization material can be applied to a substrate having a non-planar topography, such that a planar surface results. The resulting planarization layer can cover existing structures on the substrate. A top portion of the planarization layer can be solubilized using a solubility-changing agent, and then the soluble portion can be removed thereby slimming a height of the planarization material to a target value, which can be a top surface of a tallest underlying structure. With the substrate planarized, additional patterning operations can be executed.
摘要翻译：本文所述的化学平面化方法可用于平面化基板而不使用机械磨损。可显影的平面化材料可以应用于具有非平面形貌的基底，从而得到平坦的表面。所得到的平坦化层可以覆盖衬底上的现有结构。可以使用溶解度变化剂溶解平坦化层的顶部，然后可以除去可溶部分，从而将平坦化材料的高度减薄到目标值，该目标值可以是最高底层结构的顶表面。在衬底平坦化的情况下，可以执行附加的图案化操作。

99. 发明授权

US09035430B2 Semiconductor fin on local oxide 有权
标题翻译：半导体翅片局部氧化物
公开(公告)号：US09035430B2
公开(公告)日：2015-05-19
申请号：US13597799
申请日：2012-08-29
申请人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
发明人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
IPC分类号： H01L21/02 , H01L21/308 , H01L21/32 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76281 , H01L21/3081 , H01L21/3086 , H01L21/32 , H01L21/76208 , H01L29/66795 , H01L29/785
摘要： A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.
摘要翻译：提供了包括第一外延半导体层的半导体衬底。第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

100. 发明授权

US08748900B1 Re-silicide gate electrode for III-N device on Si substrate 有权
标题翻译： Si衬底上III-N器件的硅化物栅电极
公开(公告)号：US08748900B1
公开(公告)日：2014-06-10
申请号：US13851219
申请日：2013-03-27
申请人： Translucent, Inc.
发明人： Rytis Dargis , Andrew Clark , Erdem Arkun , Robin Smith , Michael Lebby
IPC分类号： H01L23/58 , H01L21/26 , H01L21/32
CPC分类号： H01L21/0254 , H01L21/02381 , H01L21/0245 , H01L21/02458 , H01L21/02488 , H01L21/02505 , H01L21/28264 , H01L29/66522 , H01L29/78
摘要： A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.
摘要翻译：在硅衬底上生长的III-N材料上制造稀土硅化物栅电极的方法包括在硅衬底上生长单晶应力补偿模板。模板基本上与硅衬底的表面晶格匹配。在模板的表面上生长单晶GaN结构，并且基本上与模板匹配的晶格。在GaN结构上生长单晶III-N材料的有源层，并且基本上与GaN结构匹配的晶格。在III-N材料的有源层上生长单晶单斜的稀土氧化物电介质层，并且在介电层硅化物上生长单晶稀土硅化物栅电极。在沉积期间调整钆金属和硅的相对部分，使其在沉积期间反应以形成稀土硅化物。

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