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1. 发明授权

US10340336B2 Power semiconductor device having fully depleted channel regions 有权
公开(公告)号：US10340336B2
公开(公告)日：2019-07-02
申请号：US15637459
申请日：2017-06-29
申请人： Infineon Technologies AG
发明人： Anton Mauder , Franz-Josef Niedernostheide , Christian Philipp Sandow
IPC分类号： H01L29/66 , H01L21/332 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/739
摘要： A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

2. 发明授权

US10325902B2 Power transistor with a plurality of bi-directional diodes 有权
公开(公告)号：US10325902B2
公开(公告)日：2019-06-18
申请号：US15247541
申请日：2016-08-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryuta Arai , Hidetoshi Asahara , Makoto Tsuzuki
IPC分类号： H01L29/66 , H01L21/332 , H01L27/02 , H01L27/06 , H01L49/02 , H01L29/10 , H01L29/78 , H01L29/87
摘要： A semiconductor device includes a first bidirectional diode of a ring shape surrounding a central region and including a first connection section and a second connection section which is provided to the inner side of the ring shape from the first connection section, a semiconductor element in the central region including a first semiconductor element electrode, a second semiconductor element electrode, and a control electrode, the first semiconductor element electrode electrically connected to the first connection section and the second semiconductor element electrode electrically connected to the control electrode, a first resistor including a first resistor electrode and a second resistor electrode, the first resistor electrode electrically connected to the second connection section and the control electrode, a second bidirectional diode electrically connected to the second resistor electrode and to the second semiconductor element electrode, and a second resistor element electrically connected to the second resistor electrode.

3. 发明授权

US09837516B2 Bi-directional punch-through semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09837516B2
公开(公告)日：2017-12-05
申请号：US15587518
申请日：2017-05-05
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Fei Yao , Shijun Wang , Bo Qin
IPC分类号： H01L21/332 , H01L29/74 , H01L29/66 , H01L29/747
CPC分类号： H01L29/7424 , H01L29/0649 , H01L29/6609 , H01L29/66386 , H01L29/747 , H01L29/861
摘要： In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

4. 发明授权

US09812561B2 Semiconductor device manufacturing method, including substrate thinning and ion implanting 有权
公开(公告)号：US09812561B2
公开(公告)日：2017-11-07
申请号：US15070429
申请日：2016-03-15
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takashi Yoshimura , Hidenao Kuribayashi , Yuichi Onozawa , Hayato Nakano , Daisuke Ozaki
IPC分类号： H01L21/332 , H01L29/739 , H01L29/08 , H01L29/36 , H01L29/66 , H01L21/265 , H01L21/285 , H01L21/324 , H01L29/06 , H01L29/10 , H01L29/167 , H01L29/423
CPC分类号： H01L29/7397 , H01L21/26513 , H01L21/2855 , H01L21/324 , H01L29/0615 , H01L29/0619 , H01L29/0804 , H01L29/0821 , H01L29/0834 , H01L29/0847 , H01L29/1004 , H01L29/1095 , H01L29/167 , H01L29/36 , H01L29/4236 , H01L29/66348 , H01L29/7395
摘要： In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm−3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.

5. 发明授权

US09461140B2 Semiconductor device manufacturing method including a counter layer for power conversion 有权
标题翻译：包括用于电力转换的计数器层的半导体器件制造方法
公开(公告)号：US09461140B2
公开(公告)日：2016-10-04
申请号：US14736532
申请日：2015-06-11
申请人： FUJI ELECTRIC CO., LTD.
发明人： Yuichi Onozawa , Takashi Shiigi
IPC分类号： H01L21/332 , H01L29/66 , H01L21/266 , H01L29/36 , H01L29/739 , H01L29/78 , H01L29/10 , H01L27/06 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66333 , H01L21/266 , H01L27/0664 , H01L29/0696 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/36 , H01L29/66325 , H01L29/66712 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L2924/13055
摘要： A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.
摘要翻译：选择性地在n型漂移层的表面上形成p型基层; n型源极层选择性地形成在p型基极层的表面上; 并且形成p型接触层以与选择形成的n型源极层接触。形成与n型源极层接触的p型对置层，以与p型接触层重叠，从而与p型基极层和栅极氧化物的界面分离膜彼此接触并且比p型基底层浅。因此，减少了由绝缘栅极半导体器件中的工艺缺陷引起的开关破坏。

6. 发明授权

US09437814B1 Mitigating damage from a chemical mechanical planarization process 有权
标题翻译：减轻化学机械平面化过程造成的损害
公开(公告)号：US09437814B1
公开(公告)日：2016-09-06
申请号：US14473879
申请日：2014-08-29
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Majid Milani , Natividad Vasquez, Jr. , Steven Patrick Maxwell , Sundar Narayanan
IPC分类号： H01L21/332 , H01L45/00
CPC分类号： H01L45/16 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.
摘要翻译：在制造双端存储器件期间，可以形成端子（例如，底端）。在端子形成之后，可以应用化学机械平面化（CMP）工艺，根据端子的组成，可以引起影响成品存储器件或电池的工作特性的损坏。在一些实施例中，可以通过一个或多个后CMP工艺来去除这种损伤。在一些实施例中，可以减轻这种损害，以便防止在完成CMP过程之前通过例如在端子顶部形成牺牲层来完全发生损坏。因此，牺牲层可以操作以保护端子免受由CMP工艺引起的损伤，在完成两端存储器件的制造之前牺牲层的其余部分被去除。

7. 发明授权

US09397207B2 Gated thyristor power device 有权
公开(公告)号：US09397207B2
公开(公告)日：2016-07-19
申请号：US14828326
申请日：2015-08-17
申请人： David Schie
发明人： David Schie
IPC分类号： H01L29/66 , H01L21/332 , H01L29/745 , H01L29/74
CPC分类号： H02M7/145 , H01L27/0921 , H01L27/1027 , H01L29/102 , H01L29/7455 , H02M7/1557 , H02M2001/4291 , H01L2924/1302 , H01L2924/13026
摘要： An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (

8. 发明授权

US09349847B2 Semiconductor device and power converter 有权
标题翻译：半导体器件和电源转换器
公开(公告)号：US09349847B2
公开(公告)日：2016-05-24
申请号：US14364959
申请日：2011-12-15
申请人： Takayuki Hashimoto , Mutsuhiro Mori
发明人： Takayuki Hashimoto , Mutsuhiro Mori
IPC分类号： H01L29/66 , H01L21/332 , H01L29/739 , H01L29/861 , H01L29/08 , H01L29/10 , H01L27/07 , H01L29/88 , H02M7/537
CPC分类号： H01L29/7397 , H01L27/0727 , H01L29/0834 , H01L29/1095 , H01L29/7395 , H01L29/861 , H01L29/88 , H02M7/537
摘要： A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n−-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n−-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n−-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n−-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip. Moreover, it is possible to avoid problems of “snap back” and “current concentration.”
摘要翻译：本发明的半导体器件（具有内置二极管的IGBT）包括：n型漂移层1; 与该n型漂移层1的表面侧接触的p型沟道区域2; 设置在沟槽T中以设置成穿过该p型沟道区域2并通过栅极绝缘膜3到达n型漂移层1的栅电极5; n型源极区域4，其设置成与p型沟道区域2的表面侧的沟槽T接触; 配置成与n型漂移层1的背面接触的高浓度n型区域6; 以及与该高浓度n型区域6的背面接触的高浓度p型区域7; 其中高浓度n型区域6和高浓度p型区域7的结是隧道结。根据该半导体器件，可以在单个芯片上形成IGBT和二极管。此外，可以避免“回弹”和“当前集中”的问题。

9. 发明授权

US09269793B2 Method and system for a gallium nitride self-aligned vertical MESFET 有权
标题翻译：氮化镓自对准垂直MESFET的方法和系统
公开(公告)号：US09269793B2
公开(公告)日：2016-02-23
申请号：US14489761
申请日：2014-09-18
申请人： Avogy, Inc.
发明人： Richard J. Brown , Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , David P. Bour
IPC分类号： H01L29/20 , H01L21/20 , H01L21/332 , H01L29/66 , H01L29/812 , H01L29/808 , H01L21/02 , H01L21/32 , H01L29/36 , H01L29/47 , H01L29/10 , H01L29/16
CPC分类号： H01L29/66856 , H01L21/0254 , H01L21/02647 , H01L21/32 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/475 , H01L29/8083 , H01L29/812 , H01L29/8122
摘要： A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.
摘要翻译：半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。半导体衬底还包括耦合到漂移区的沟道区。通道区域由基本沿着生长方向设置的通道侧壁限定。半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

10. 发明授权

US09245950B2 Method for fabricating an insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管的制造方法
公开(公告)号：US09245950B2
公开(公告)日：2016-01-26
申请号：US14537148
申请日：2014-11-10
申请人： Takuma Kamijo
发明人： Takuma Kamijo
IPC分类号： H01L21/332 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/739 , H01L27/07
CPC分类号： H01L29/0821 , H01L27/0727 , H01L29/0873 , H01L29/1095 , H01L29/6609 , H01L29/66136 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397 , H01L29/8613 , H01L2924/10155 , H01L2924/13055
摘要： A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the IGBT, and a second buffer region adjacent to the collector region at the rear surface side. The method includes forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate, and injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed.
摘要翻译：提供一种制造半导体器件的方法。半导体器件包括二极管的阴极区域，与半导体衬底的背面侧的阴极区域相邻的第一缓冲区域，IGBT的集电极区域和与后部的集电极区域相邻的第二缓冲区域表面该方法包括在前表面上形成阶梯部分，使得半导体衬底中形成薄壁部分和厚壁部分，并将n型杂质注入到延伸穿过薄壁部分的前表面上的范围内，使得形成第一缓冲区域和第二缓冲区域。

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