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91. 发明授权

US06872648B2 Reduced splattering of unpassivated laser fuses 有权
标题翻译：降低未激活的激光保险丝的飞溅
公开(公告)号：US06872648B2
公开(公告)日：2005-03-29
申请号：US10246999
申请日：2002-09-19
申请人： Gerald R. Friese , Andy Cowley , Mohammed Fazil Fayaz , William T. Motsiff
发明人： Gerald R. Friese , Andy Cowley , Mohammed Fazil Fayaz , William T. Motsiff
IPC分类号： H01L23/525 , H01L21/71
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.
摘要翻译：使用激光器吹动未激活的电熔丝（例如，熔丝405）的行为可能导致熔丝材料的飞溅并导致电气短路。形成在由激光器熔断的熔丝区域周围形成的防爆屏障（例如鼓风屏障406）有助于容纳熔丝材料的飞溅。防爆屏障可以由与熔丝本身相同的材料形成，因此可以在相同的制造步骤中形成。

92. 发明授权

US5997757A Method of forming connection hole 失效
标题翻译：形成连接孔的方法
公开(公告)号：US5997757A
公开(公告)日：1999-12-07
申请号：US653453
申请日：1996-05-24
申请人： Tetsuji Nagayama , Masaki Minami
发明人： Tetsuji Nagayama , Masaki Minami
IPC分类号： H05H1/46 , C23F4/00 , C30B33/12 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L21/71 , H01L21/308 , H01L21/769
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76829 , H01L21/823425 , H01L2924/3011 , Y10T428/31909
摘要： A method of forming a connection hole, which includes the steps of: laminating an etching stopper film made of a SiN based material and an interlayer insulating film made of a SiOx based material on a substrate in this order; forming an organic film pattern on the interlayer insulating film on the basis of a connection hole pattern; dry-etching the interlayer insulating film using the organic film pattern as a mask while keeping a selection ratio to the etching stopper film; a fourth step of removing a carbon based protective film which is deposited on an exposed surface of the etching stopper film by the dry etching, using an etching reactive system including an oxygen based chemical species; and a fifth step of completing a connection hole by selectively etching the etching stopper film.
摘要翻译：一种形成连接孔的方法，包括以下步骤：将由SiN基材料制成的蚀刻阻挡膜和由SiOx基材料制成的层间绝缘膜依次层压在基板上; 基于连接孔图案在层间绝缘膜上形成有机膜图案; 使用有机膜图案作为掩模来干蚀刻层间绝缘膜，同时保持与蚀刻停止膜的选择比; 通过使用包含氧基化学物质的蚀刻反应系统，通过干蚀刻去除沉积在蚀刻阻挡膜的暴露表面上的碳基保护膜的第四步骤; 以及通过选择性地蚀刻蚀刻停止膜来完成连接孔的第五步骤。

93. 发明授权

US5532186A Process for manufacturing bumped tab tape 失效
标题翻译：冲压片胶带的制造工艺
公开(公告)号：US5532186A
公开(公告)日：1996-07-02
申请号：US319486
申请日：1994-10-07
申请人： Yasushi Kobayashi
发明人： Yasushi Kobayashi
IPC分类号： H01L21/60 , H01L21/48 , H01L23/498 , H05K3/34 , H05K3/36 , H01L21/71
CPC分类号： H01L21/4853 , H01L23/49816 , H05K3/3426 , H01L2924/0002 , H05K2201/09745 , H05K2201/10681 , H05K2201/10984 , H05K2203/041 , H05K2203/043 , H05K3/3484 , H05K3/363 , Y02P70/613 , Y10T29/49121
摘要： A manufacturing method for a TAB tape which forms a plurality of bumps on a plurality of sheet-like leads of the TAB tape. First, the leads are fixed to a belt-shaped tape member having a plurality of first openings arranged at equal intervals in a longitudinal direction and a plurality of second openings formed around each of the first openings. In fixing each lead to the tape member, one end portion of the lead is exposed to each first opening, and the other end portion of the lead is exposed to each second opening. Secondly, a point is pressed onto a surface of each lead to form a plurality of recesses on the surface of each lead. Thirdly, a metal ball is seated in each recess, and is then heated to be molten so that a part of the metal ball may substantially semispherically project from the surface of the lead. Thus, a metal bump is formed as a substantially semispherical part projecting from the surface of each lead. Instead of the use of the metal ball, a mixture of a metal powder and a paste may be filled in each recess. In this case, the mixture filled in each recess is heated to be molten so that a part of the mixture may substantially semispherically project from the surface of each lead, thus forming the metal bumps on the surface of each lead.
摘要翻译：一种在TAB带的多个片状引线上形成多个凸块的TAB带的制造方法。首先，将引线固定在带状带状部件上，该带状部件具有沿纵向相等间隔排列的多个第一开口和围绕每个第一开口形成的多个第二开口。在将每个引线固定到带构件上时，引线的一个端部暴露于每个第一开口，并且引线的另一端部暴露于每个第二开口。其次，将点压在每个引线的表面上，以在每个引线的表面上形成多个凹槽。第三，将金属球放置在每个凹槽中，然后被加热熔化，使得金属球的一部分可以从铅的表面基本上半径地突出。因此，金属凸块形成为从每个引线的表面突出的大致半球形部分。代替使用金属球，可以在每个凹部中填充金属粉末和糊料的混合物。在这种情况下，填充在每个凹部中的混合物被加热熔化，使得该混合物的一部分可以从每个引线的表面基本上半径地突出，从而在每个引线的表面上形成金属凸块。

94. 发明申请

US20230139898A1 IC HAVING ELECTRICALLY ISOLATED WARPAGE PREVENTION STRUCTURES 有权
公开(公告)号：US20230139898A1
公开(公告)日：2023-05-04
申请号：US17512958
申请日：2021-10-28
申请人： Texas Instruments Incorporated
发明人： Christlyn Faith Hobrero Arias , Rafael Jose Lizares Guevara
IPC分类号： H01L23/00 , H01L23/31 , H01L21/71
摘要： Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.

95. 发明申请

US20230043166A1 SEAL RING REINFORCEMENT 有权
公开(公告)号：US20230043166A1
公开(公告)日：2023-02-09
申请号：US17716444
申请日：2022-04-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yen Lian Lai , Chun Yu Chen
IPC分类号： H01L23/58 , H01L23/00 , H01L21/71
摘要： Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.

96. 再颁专利

USRE49059E1 Stressed substrates for transient electronic systems 有权
公开(公告)号：USRE49059E1
公开(公告)日：2022-05-03
申请号：US16537258
申请日：2019-08-09
申请人： Palo Alto Research Center Incorporated
发明人： Scott J. H. Limb , Gregory L. Whiting , Sean R. Garner , JengPing Lu , Dirk De Bruyker
IPC分类号： H01L21/64 , H01L21/71 , H01L23/14 , H01L27/00 , H03K19/177 , H03K19/17768
摘要： A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

97. 发明授权

US11088148B2 Semiconductor memory devices including separate upper and lower bit line spacers 有权
公开(公告)号：US11088148B2
公开(公告)日：2021-08-10
申请号：US16509820
申请日：2019-07-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Daeik Kim , Semyeong Jang , Jemin Park , Yoosang Hwang
IPC分类号： H01L27/108 , H01L21/28 , H01L29/792 , H01L21/71 , H01L21/8234
摘要： A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

98. 发明授权

US10388561B2 Semiconductor integrated circuit device having electrostatic discharge protection circuit 有权
公开(公告)号：US10388561B2
公开(公告)日：2019-08-20
申请号：US15613780
申请日：2017-06-05
申请人： SK hynix Inc.
发明人： Yun Seok Hong
IPC分类号： H05F3/02 , H01L21/71 , H01L21/74 , H01L27/02 , H01L27/24 , H01L45/00
摘要： A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line.

99. 发明申请

US20180286870A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATE UPPER AND LOWER BIT LINE SPACERS 审中-公开
公开(公告)号：US20180286870A1
公开(公告)日：2018-10-04
申请号：US15845141
申请日：2017-12-18
申请人： Samsung Electronics Co., Ltd.
发明人： Daeik Kim , Semyeong Jang , Jemin Park , Yoosang Hwang
IPC分类号： H01L27/108 , H01L29/792 , H01L21/28 , H01L21/71
CPC分类号： H01L27/10885 , H01L21/28273 , H01L21/71 , H01L21/823475 , H01L27/10808 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10882 , H01L29/40114 , H01L29/7926
摘要： A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

100. 发明申请

US20170352688A1 Method of Manufacturing Thin Film Transistor, Dehydrogenating Apparatus for Performing the Same, and Organic Light Emitting Display Device Including Thin Film Transistor Manufactured by the Same 审中-公开
公开(公告)号：US20170352688A1
公开(公告)日：2017-12-07
申请号：US15595463
申请日：2017-05-15
申请人： LG Display Co., Ltd.
发明人： Sung soo LEE
IPC分类号： H01L27/12 , H01L21/70 , H01L21/02 , H01L21/71 , H01L29/786 , H01L29/06
CPC分类号： H01L27/1214 , H01L21/02107 , H01L21/02488 , H01L21/02532 , H01L21/02595 , H01L21/02675 , H01L21/707 , H01L21/71 , H01L27/1259 , H01L29/0653 , H01L29/66757 , H01L29/786
摘要： Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

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