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91. 发明授权

US08134196B2 Integrated circuit system with metal-insulator-metal circuit element 有权
标题翻译：具有金属绝缘体金属电路元件的集成电路系统
公开(公告)号：US08134196B2
公开(公告)日：2012-03-13
申请号：US11469576
申请日：2006-09-01
申请人： Yaojian Lin , Haijing Cao , Wan Lay Looi , Eng Seng Lim
发明人： Yaojian Lin , Haijing Cao , Wan Lay Looi , Eng Seng Lim
IPC分类号： H01L29/76 , H01L21/8242
CPC分类号： H01L28/75
摘要： An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact on the dielectric layer and over the first contact.
摘要翻译：提供一种集成电路系统，包括形成衬底，在衬底上形成具有多个导电层的第一触点和在多个导电层的其它层上的多个导电层的层，在第一触点上形成电介质层，以及形成在介电层上和第一接触点上的第二接触。

92. 发明授权

US08133772B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US08133772B2
公开(公告)日：2012-03-13
申请号：US13075271
申请日：2011-03-30
申请人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

93. 发明授权

US08124475B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US08124475B2
公开(公告)日：2012-02-28
申请号：US12414120
申请日：2009-03-30
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。

94. 发明授权

US08114732B2 Method for manufacturing twin bit structure cell with Al2O3/nano-crystalline Si layer 有权
标题翻译：用Al2O3 /纳米晶硅层制造双位结构电池的方法
公开(公告)号：US08114732B2
公开(公告)日：2012-02-14
申请号：US12704502
申请日：2010-02-11
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L21/336 , H01L21/461 , H01L21/8242
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7887
摘要： A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure.
摘要翻译：一种用于形成非易失性存储器结构的方法和系统。该方法包括提供半导体衬底并形成覆盖在半导体衬底的表面区域上的栅极电介质层。形成覆盖栅极电介质层的多晶硅栅极结构。该方法使多晶硅栅极结构进入氧化环境，以形成覆盖多晶硅栅极结构的第一氧化硅层和在多晶硅栅极结构下方形成底切区域。在填充底切区域的多晶硅栅极结构之上形成氧化铝材料。在具体实施方案中，氧化铝材料具有夹在第一氧化铝层和第二氧化铝层之间的纳米晶硅材料。对氧化铝材料进行选择性蚀刻处理，同时将氧化铝材料保持在切削区域的一部分中的插入区域中。该方法形成覆盖多晶硅栅极结构的侧面区域的侧壁结构。

95. 发明授权

US08084323B2 Stack capacitor of memory device and fabrication method thereof 有权
标题翻译：存储器件的堆叠电容器及其制造方法
公开(公告)号：US08084323B2
公开(公告)日：2011-12-27
申请号：US12640846
申请日：2009-12-17
申请人： Shin-Yu Nieh
发明人： Shin-Yu Nieh
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/1085
摘要： The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
摘要翻译：本发明提供了一种用于形成存储器件的堆叠电容器的方法，包括提供衬底，在衬底上形成具有多个第一开口的图案化牺牲层，在图案化的牺牲层上和第一层中共形形成第一导电层开口，在第一导电层上形成第二导电层，以密封其中形成的空隙的第一开口，去除第一和第二导电层的一部分以暴露图案化的牺牲层，以及去除图案化牺牲层的至少一部分层形成底细胞板。

96. 发明授权

US08084322B2 Method of manufacturing devices having vertical junction edge 有权
标题翻译：制造具有垂直接合边缘的器件的方法
公开(公告)号：US08084322B2
公开(公告)日：2011-12-27
申请号：US11440260
申请日：2006-05-24
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L21/8242
CPC分类号： H01L29/66636 , H01L21/2257 , H01L21/823481 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/7834
摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
摘要翻译：用于形成诸如晶体管的器件的技术具有垂直的接合边缘。更具体地说，在沟槽中形成浅沟槽并填充氧化物。可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

97. 发明授权

US08080457B1 Fabrication method of power semiconductor structure with low gate charge 有权
标题翻译：具有低栅极电荷的功率半导体结构的制造方法
公开(公告)号：US08080457B1
公开(公告)日：2011-12-20
申请号：US12917498
申请日：2010-11-02
申请人： Hsiu-Wen Hsu
发明人： Hsiu-Wen Hsu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L21/20
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.
摘要翻译：提供了具有低栅极电荷的沟槽功率半导体结构的制造方法。首先，提供基板。然后，在衬底中形成栅极沟槽。之后，在栅极沟槽的内表面上形成介电层。然后，在覆盖栅极沟槽的侧壁的电介质层上形成间隔物。此后，在由间隔物限定的栅极沟槽的底部的空间中形成插塞结构。然后，用电介质结构和插塞结构作为蚀刻掩模去除间隔物的一部分。此后，用剩余的间隔物去除介电层的一部分作为蚀刻掩模，以露出栅极沟槽的上部的内表面。之后，保持留着的间隔物，在栅极沟槽的上部的内表面上形成栅极电介质层，然后将多晶硅栅极填充到栅极沟槽的上部。

98. 发明授权

US08076213B2 Method for fabricating a metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器的制造方法
公开(公告)号：US08076213B2
公开(公告)日：2011-12-13
申请号：US12554968
申请日：2009-09-07
申请人： Lian-Hua Shih , Yi-Ching Wu , Jiann-Fu Chen , Ming-Te Chen , Chin-Jen Cheng
发明人： Lian-Hua Shih , Yi-Ching Wu , Jiann-Fu Chen , Ming-Te Chen , Chin-Jen Cheng
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , Y10S438/957
摘要： A method for fabricating a metal-insulator-metal (MIM) capacitor includes providing a substrate comprising a bottom electrode, forming a dielectric layer positioned on the bottom electrode, and forming a top electrode positioned on the dielectric layer. The dielectric layer includes a silicon nitride film, the silicon nitride film has a plurality of Si—H bonds and a plurality of N—H bonds, and a ratio of Si—H bonds to N—H bonds being equal to or smaller than 0.5.
摘要翻译：一种用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法，包括提供包括底部电极的基板，形成位于所述底部电极上的电介质层，以及形成位于所述电介质层上的顶部电极。介电层包括氮化硅膜，氮化硅膜具有多个Si-H键和多个N-H键，Si-H键与N-H键的比例等于或小于0.5 。

99. 发明授权

US08071439B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08071439B2
公开(公告)日：2011-12-06
申请号：US12461313
申请日：2009-08-07
申请人： Toshiyuki Hirota
发明人： Toshiyuki Hirota
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/76816 , H01L27/10817 , H01L27/10852
摘要： A method for manufacturing a semiconductor device includes forming a first interlayer insulating film over a semiconductor substrate; forming a first opening in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film such that the first opening is not filled; and forming a second opening in the second interlayer insulating film such that the second opening is connected to the first opening.
摘要翻译：一种半导体器件的制造方法包括在半导体衬底上形成第一层间绝缘膜; 在所述第一层间绝缘膜中形成第一开口; 在所述第一层间绝缘膜上形成第二层间绝缘膜，使得所述第一开口未被填充; 以及在所述第二层间绝缘膜中形成第二开口，使得所述第二开口连接到所述第一开口。

100. 发明申请

US20110291170A1 Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level 有权
标题翻译：包括在接触层中形成的埋地电容器的半导体器件
公开(公告)号：US20110291170A1
公开(公告)日：2011-12-01
申请号：US12965212
申请日：2010-12-10
申请人： Dmytro Chumakov , Tino Hertzsch
发明人： Dmytro Chumakov , Tino Hertzsch
IPC分类号： H01L27/108 , H01L21/20 , H01L21/8242
CPC分类号： H01L27/0629 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.
摘要翻译：在半导体器件中，可以通过使用诸如漏极区域或紧密间隔的晶体管的源极区域的共享晶体管区域作为一个电容器电极来形成电容器以与晶体管直接接触，而另一个电容器电极以接触电平的电介质材料中的埋入电极的形式提供。为此，可以沉积电介质材料以便可靠地形成空隙，其中，在任何适当的制造阶段，可以提供电容器电介质材料以分离电容器电极。

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