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11. 发明授权

US09330786B2 Semiconductor device, test method thereof, and system 有权
标题翻译：半导体器件，其测试方法和系统
公开(公告)号：US09330786B2
公开(公告)日：2016-05-03
申请号：US13012360
申请日：2011-01-24
申请人： Satoshi Uetake , Yuji Uo
发明人： Satoshi Uetake , Yuji Uo
IPC分类号： G01R31/28 , G11C29/40 , G11C5/04
CPC分类号： G11C29/40 , G11C5/04 , H01L2224/16 , H01L2924/1305 , H01L2924/00
摘要： A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.
摘要翻译：半导体器件包括多个芯片，其包括多个通过通孔电极共同连接的I / O端子。每个芯片包括I / O压缩电路，其可操作以将通过将多个内部数据总线的数据压缩获得的压缩结果输出到多个I / O端子的第一I / O端子。每个芯片还包括具有设置第一I / O端子的数量的寄存器组的测试控制电路。在寄存器组中设置了将不同的第一个I / O端子分配给不同的芯片的设置信息。每个芯片使用不同于其他芯片中的I / O端子的数量来输入或输出数据。因此，I / O压缩电路可以并行地在多个芯片中并行执行I / O压缩测试，而不需要总线作战。

12. 再颁专利

USRE45932E1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：USRE45932E1
公开(公告)日：2016-03-15
申请号：US14278877
申请日：2014-05-15
申请人： PS4 Luxco S.a.r.l.
发明人： Seiya Fujii
IPC分类号： H01L23/52 , H01L23/498 , H01L21/60
CPC分类号： H01L23/49838 , H01L21/561 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L2221/68331 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4911 , H01L2224/83191 , H01L2224/85205 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06586 , H01L2924/014 , H01L2924/07802 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H05K3/3436 , H05K2201/09781 , Y02P70/613 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.

13. 发明申请

US20160071843A1 Semiconductor Device and Method of Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160071843A1
公开(公告)日：2016-03-10
申请号：US14943595
申请日：2015-11-17
申请人： PS4 Luxco S.a.r.l.
发明人： Tomohiro Kadoya
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/76895 , H01L21/823475 , H01L27/0207 , H01L27/10852 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L28/91
摘要： A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
摘要翻译：半导体器件包括以下元件。元件隔离部分分离半导体衬底中的第一和第二扩散区域。第一绝缘膜形成在元件隔离部分和第一和第二扩散区域上。第一和第二接触塞分别形成在第一和第二扩散区上。第一和第二接触插塞穿透第一绝缘膜。在元件隔离部分上方的第一绝缘膜上形成第一导电层。在第一导电层上形成第二绝缘膜。第三接触插塞穿透第二绝缘膜，第三接触插塞连接第一接触插塞。在与第三接触插塞接触的第二绝缘膜上形成第二导电层。第一和第二导电层部分地与元件隔离部分重叠。

14. 发明授权

US09281050B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US09281050B2
公开(公告)日：2016-03-08
申请号：US14564219
申请日：2014-12-09
申请人： PS4 LUXCO S.A.R.L.
发明人： Chikara Kondo
IPC分类号： G11C5/02 , G11C11/409 , G11C5/06 , G11C11/4063 , G11C11/4076
CPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C11/4063 , G11C11/4076 , H01L2224/16145
摘要： A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.
摘要翻译：一种用于从连接到公共命令，地址和数据总线的多个DRAM装置读取数据的方法。时钟信号被提供给多个DRAM设备。在命令和地址总线上与时钟信号同步的多个DRAM设备的读命令和地址。读取时钟信号被提供给多个DRAM设备以在由该地址选择的多个DRAM设备之一中启动读取操作。一个DRAM器件基于多个DRAM器件中的一个DRAM器件的速度来延迟读取时钟信号的量以产生。提供第一延迟读时钟和第二延迟读时钟信号。与第二延迟读时钟信号同步地在数据总线上接收读数据。

15. 发明授权

US09276465B2 Switching regulator detecting abnormality in power supply voltage 有权
标题翻译：开关稳压器检测电源电压异常
公开(公告)号：US09276465B2
公开(公告)日：2016-03-01
申请号：US13137970
申请日：2011-09-22
申请人： Yuji Hidaka
发明人： Yuji Hidaka
IPC分类号： G05F1/56 , H02M3/156
CPC分类号： H02M3/156
摘要： A switching regulator includes: a switching element that controlling supply of power supply voltage according to a control signal; a smoothing circuit smoothing the power supply voltage supplied via the switching element and supplying the smoothed power supply voltage as an output voltage to an output terminal; an error amplifier outputting an error signal according to a difference between the output voltage supplied to the output terminal and a reference voltage; a delta sigma modulation circuit generating a delta sigma modulation signal according to the error signal; and a power supply abnormality detection circuit outputting the delta sigma modulation signal as the control signal and detecting an abnormality in the power supply voltage based on the delta sigma modulation signal.
摘要翻译：开关调节器包括：根据控制信号控制供电电压的开关元件; 平滑电路，平滑经由开关元件提供的电源电压，并将平滑的电源电压作为输出电压提供给输出端; 误差放大器，根据提供给输出端子的输出电压与参考电压之差，输出误差信号; ΔΣ调制电路根据误差信号产生ΔΣ调制信号; 以及电源异常检测电路，输出所述Δ-Σ调制信号作为所述控制信号，并基于所述Δ-Σ调制信号检测所述电源电压的异常。

16. 发明授权

US09269458B2 Semiconductor device enabling refreshing of redundant memory cell instead of defective memory cell 有权
标题翻译：半导体器件能够刷新冗余存储器单元而不是有缺陷的存储器单元
公开(公告)号：US09269458B2
公开(公告)日：2016-02-23
申请号：US14531311
申请日：2014-11-03
申请人： PS4 Luxco S.a.r.l.
发明人： Yuki Hosoe
IPC分类号： G11C29/00 , G11C29/08 , G11C29/04 , G11C11/406
CPC分类号： G11C29/08 , G11C11/406 , G11C29/04
摘要： A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal memory cell NMC that belongs to at least one of memory blocks MB1 and MB2 being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit 25 deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs.
摘要翻译：半导体器件包括可以进入访问存储器块MB1或存储器块MB2的正常操作模式的存储器块MB1和MB2以及同时访问存储器块MB1和存储器块MB2的刷新模式的存储器块MB1和MB2以及冗余确定电路25。响应于在刷新模式下属于由冗余存储器单元RMC替换的存储器块MB1和MB2中的至少一个的正常存储器单元NMC，冗余确定电路25使作为源的正常存储单元NMC的正常单元区域NCA去激活并且激活要被替换的冗余存储器单元RMC所属的冗余单元区域RCA以及未被替换的正常存储单元NMC所属的正常单元区域NCA。

17. 发明授权

US09252126B2 Multi Chip Package-type semiconductor device 有权
标题翻译：多芯片封装型半导体器件
公开(公告)号：US09252126B2
公开(公告)日：2016-02-02
申请号：US13796903
申请日：2013-03-12
申请人： PS4 Luxco S.a.r.l.
发明人： Atsushi Tomohiro
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/00 , H01L23/00 , H01L25/065 , H01L23/31 , H01L21/56
CPC分类号： H01L25/00 , H01L21/561 , H01L23/3128 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06562 , H01L2225/06568 , H01L2225/06575 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/85 , H01L2924/00012
摘要： A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.
摘要翻译：一种半导体器件包括布线板，经由第一粘合部件安装在布线板上的第一半导体芯片，以及经由第二粘合部件堆叠在第一半导体芯片上的第二半导体芯片。第一粘合剂是具有在绝缘基材的两面上形成的粘合剂层的管芯附着膜，第二粘合部件是粘合剂糊剂。

18. 再颁专利

USRE45861E1 Semiconductor memory using field-effect transistor as selective element 有权
标题翻译：半导体存储器采用场效应晶体管作为选择元件
公开(公告)号：USRE45861E1
公开(公告)日：2016-01-19
申请号：US14639672
申请日：2015-03-05
申请人： PS4 Luxco S.a.r.l.
发明人： Shuichi Tsukada , Yasuhiro Uchiyama
IPC分类号： H01L47/00 , H01L27/24
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/2463 , H01L45/06
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，嵌入在半导体衬底上形成的沟槽中的第一绝缘膜区域，覆盖第一绝缘膜区域的下表面的栅电极和栅极绝缘膜设置在栅电极和半导体衬底之间。半导体器件还包括覆盖第一绝缘膜区域的第一侧面的第一扩散区域和覆盖第一绝缘膜区域的第二侧面的第二扩散区域和覆盖第一绝缘膜区域的上表面的第三扩散区域第二扩散区。选择元件包括由栅电极，第一扩散区和第二扩散区构成的场效应晶体管，以及由衬底和第二和第三扩散区构成的双极晶体管。

19. 发明授权

US09218871B2 Semiconductor memory device, information processing system including the same, and controller 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US09218871B2
公开(公告)日：2015-12-22
申请号：US14155993
申请日：2014-01-15
申请人： PS4 Luxco S.a.r.l.
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C5/06 , G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
摘要翻译：分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

20. 发明申请

US20150364181A1 OUTPUT SIGNAL GENERATING DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SIGNAL GENERATION METHOD 有权
标题翻译：输出信号发生装置，半导体装置和输出信号发生方法
公开(公告)号：US20150364181A1
公开(公告)日：2015-12-17
申请号：US14761557
申请日：2014-01-15
申请人： PS4 Luxco S.a.r.l.
发明人： Kazutaka Miyano
IPC分类号： G11C11/4076 , H03K5/24 , G11C7/10 , H03L7/081 , G11C11/4093 , G11C11/4074
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C11/4074 , G11C11/4093 , H03K5/24 , H03L7/0812 , H03L7/0814
摘要： An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.
摘要翻译：根据所公开的实施例的输出信号产生装置包括：相位调整单元，其基于输入信号生成输出信号，并且能够执行将输入信号和输出信号之间的相位差设置为预定值保持基准电压的保持单元; 比较电压产生单元，其生成取决于电源电压的比较电压; 以及控制单元，其间歇地比较保持在保持单元中的参考电压的比较电压，当比较结果满足表示电源电压变化的预定条件时，使相位调整电路执行调整操作，参考电压根据电源电压保持在保持单元中。

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