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11. 发明申请

US20130069143A1 TRENCH TYPE POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： TRENCH型功率晶体管器件及其制造方法
公开(公告)号：US20130069143A1
公开(公告)日：2013-03-21
申请号：US13237940
申请日：2011-09-21
申请人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , SUNG-SHAN TAI
发明人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , SUNG-SHAN TAI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.
摘要翻译：本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。半导体衬底具有至少一个沟槽。晶体管单元包括设置在沟槽中的第一栅极导电层。栅极金属层和源极金属层设置在半导体衬底上。第二栅极导电层设置在第一栅极导电层和源极金属层之间。第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

12. 发明申请

US20130049104A1 Method of forming a self-aligned contact opening in MOSFET 有权
标题翻译：在MOSFET中形成自对准接触开口的方法
公开(公告)号：US20130049104A1
公开(公告)日：2013-02-28
申请号：US13218476
申请日：2011-08-26
申请人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
发明人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
摘要翻译：提出了在半导体衬底中形成接触开口的方法。在半导体衬底中形成各自具有突出部分的多个沟槽栅极，并且在突出部分上延伸的半导体衬底上沉积停止层，其中沿着突出部分的每个侧壁的阻挡层的每个部分是被间隔物覆盖。通过利用阻挡层对间隔物的相对较高的蚀刻选择性去除未被间隔物覆盖的停止层的部分，可以形成每个侧壁上具有L型形状的相邻突出部分之间的开口，并且可以形成光刻此后可以进行处理以形成自对准的接触开口。

13. 发明授权

US09368621B1 Power semiconductor device having low on-state resistance 有权
标题翻译：具有低导通电阻的功率半导体器件
公开(公告)号：US09368621B1
公开(公告)日：2016-06-14
申请号：US14555518
申请日：2014-11-26
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： Po-Hsien Li , Guo-Liang Yang
IPC分类号： H01L29/06 , H01L29/78 , H01L29/73 , H01L29/40 , H01L29/423 , H01L29/417 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095 , H01L29/407 , H01L29/7397 , H01L29/7811
摘要： A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.
摘要翻译：具有低导通电阻的功率半导体器件包括其上形成有外延层的衬底，栅极结构，端接结构和图案化导电层。外延层具有至少第一沟槽和第二沟槽。栅极结构嵌入在第一沟槽中，包括设置在栅电极下方的栅电极和屏蔽电极。端接结构嵌入在第二沟槽中，包括端接电极。图案化的导电层设置在外延层的上方。特别地，栅极结构的屏蔽电极和终端结构的终端电极被配置为接收栅极电压。图案化导电层被配置为分别通过第一接触插塞和第二接触插塞电接触所述栅电极和端接电极。

14. 发明授权

US09166037B2 Power semiconductor device with electrostatic discharge structure 有权
标题翻译：功率半导体器件具有静电放电结构
公开(公告)号：US09166037B2
公开(公告)日：2015-10-20
申请号：US13101155
申请日：2011-05-05
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L27/02 , H01L29/78 , H01L29/66 , H01L29/06 , H01L29/417
CPC分类号： H01L29/7813 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L29/0653 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7808
摘要： A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.
摘要翻译：具有静电放电（ESD）结构的功率半导体器件包括N型半导体衬底，至少一个ESD器件和至少一个沟槽型晶体管器件。 N型半导体具有至少两个沟槽，并且ESD器件设置在沟槽之间的N型半导体衬底中。 ESD器件包括P型第一掺杂区域和设置在P型第一掺杂区域中的N型第二掺杂区域和N型第三掺杂区域。 N型第二掺杂区域电连接到沟槽型晶体管器件的栅极，并且N型第三掺杂区域电连接到沟槽型晶体管器件的漏极。

15. 发明授权

US08680609B2 Depletion mode semiconductor device with trench gate and manufacturing method thereof 有权
标题翻译：具有沟槽栅的缺陷模式半导体器件及其制造方法
公开(公告)号：US08680609B2
公开(公告)日：2014-03-25
申请号：US13091160
申请日：2011-04-21
申请人： Wei-Chieh Lin , Jia-Fu Lin
发明人： Wei-Chieh Lin , Jia-Fu Lin
IPC分类号： H01L29/76
CPC分类号： H01L29/7828 , H01L21/26586 , H01L29/41766 , H01L29/66666
摘要： A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.
摘要翻译：耗尽型沟槽半导体器件的制造方法包括以下步骤。首先，提供包括设置在其上的漂移外延层的衬底。沟槽设置在漂移外延层中。栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。形成薄的掺杂区域并保形地接触栅极电介质层。形成栅极材料层以填充沟槽。源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。

16. 发明授权

US08564097B2 Reverse conducting IGBT 失效
标题翻译：反向导通IGBT
公开(公告)号：US08564097B2
公开(公告)日：2013-10-22
申请号：US12760754
申请日：2010-04-15
申请人： Florin Udrea , Chih-Wei Hsu , Wei-Chieh Lin
发明人： Florin Udrea , Chih-Wei Hsu , Wei-Chieh Lin
IPC分类号： H01L27/082
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/66348
摘要： An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.
摘要翻译：提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

17. 发明授权

US08319284B2 Laterally diffused metal-oxide-semiconductor device 有权
标题翻译：横向扩散金属氧化物半导体器件
公开(公告)号：US08319284B2
公开(公告)日：2012-11-27
申请号：US12839426
申请日：2010-07-20
申请人： Wei-Chieh Lin , Ho-Tai Chen , Jia-Fu Lin , Po-Hsien Li
发明人： Wei-Chieh Lin , Ho-Tai Chen , Jia-Fu Lin , Po-Hsien Li
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/0878 , H01L29/402 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/456 , H01L29/7816 , H01L29/7835
摘要： A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.
摘要翻译：横向扩散的金属氧化物半导体器件包括衬底，栅极电介质层，栅极多晶硅层，源极区域，漏极区域，体区域，第一漏极接触插塞，源极多晶硅层，绝缘层，和源极金属层。设置在漏极区域上的栅极电介质层上的源极多晶硅层可以用作场板，以增强击穿电压并增加漏极 - 源极电容。此外，本发明的第一漏极接触插塞可以减小漏极 - 源极导通电阻和水平延长长度。

18. 发明授权

US10128368B2 Double gate trench power transistor and manufacturing method thereof 有权
公开(公告)号：US10128368B2
公开(公告)日：2018-11-13
申请号：US14994250
申请日：2016-01-13
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： Po-Hsien Li , Jia-Fu Lin , Chia-Cheng Chen , Wei-Chieh Lin
IPC分类号： H01L29/78 , H01L29/40 , H01L29/10 , H01L29/66
摘要： A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.

19. 发明授权

US09722071B1 Trench power transistor 有权
公开(公告)号：US09722071B1
公开(公告)日：2017-08-01
申请号：US15005130
申请日：2016-01-25
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： Po-Hsien Li , Guo-Liang Yang , Jia-Fu Lin , Wei-Chieh Lin
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/40 , H01L29/10 , H01L29/08 , H01L23/29 , H01L23/31
CPC分类号： H01L29/7813 , H01L23/291 , H01L23/3171 , H01L23/3178 , H01L23/3192 , H01L29/0619 , H01L29/0865 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.

20. 发明授权

US08963235B1 Trench power device and semiconductor structure thereof 有权
标题翻译：沟槽功率器件及其半导体结构
公开(公告)号：US08963235B1
公开(公告)日：2015-02-24
申请号：US14063061
申请日：2013-10-25
申请人： Sinopower Semiconductor, Inc.
发明人： Po-Hsien Li
IPC分类号： H01L29/66 , H01L29/423 , H01L29/47 , H01L29/78
CPC分类号： H01L29/47 , H01L29/407 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/8725
摘要： A semiconductor structure of a trench power device comprises a base, an insulating layer, and a source conductive layer. The base includes a first trench etched from the top surface thereof, and two portions of the top surface arranged at two opposite sides of the first trench are respectively defined as two top contacting surfaces. Part of the first trench is filled with the insulating layer, and two inner walls of a non-filled portion of the first trench are respectively defined as two side contacting surfaces without contacting the insulating layer. The source conductive layer is embedded in the insulating layer. Thus, when a metallic layer is integrally formed on the semiconductor structure and connects the top contacting surfaces and the side contacting surfaces, the top contacting surfaces and the side contacting surfaces are configured to be a Schottky barrier interface.
摘要翻译：沟槽功率器件的半导体结构包括基极，绝缘层和源极导电层。基底包括从其顶表面蚀刻的第一沟槽，并且布置在第一沟槽的两个相对侧的顶表面的两个部分分别限定为两个顶部接触表面。第一沟槽的一部分填充有绝缘层，并且第一沟槽的未填充部分的两个内壁分别被限定为不接触绝缘层的两个侧接触表面。源极导电层嵌入绝缘层。因此，当在半导体结构上整体形成金属层并连接顶部接触表面和侧面接触表面时，顶部接触表面和侧面接触表面被构造为肖特基势垒界面。

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