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    • 2. 发明授权
    • Power semiconductor device having low on-state resistance
    • 具有低导通电阻的功率半导体器件
    • US09368621B1
    • 2016-06-14
    • US14555518
    • 2014-11-26
    • SINOPOWER SEMICONDUCTOR, INC.
    • Po-Hsien LiGuo-Liang Yang
    • H01L29/06H01L29/78H01L29/73H01L29/40H01L29/423H01L29/417H01L29/739
    • H01L29/7813H01L29/0634H01L29/1095H01L29/407H01L29/7397H01L29/7811
    • A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.
    • 具有低导通电阻的功率半导体器件包括其上形成有外延层的衬底,栅极结构,端接结构和图案化导电层。 外延层具有至少第一沟槽和第二沟槽。 栅极结构嵌入在第一沟槽中,包括设置在栅电极下方的栅电极和屏蔽电极。 端接结构嵌入在第二沟槽中,包括端接电极。 图案化的导电层设置在外延层的上方。 特别地,栅极结构的屏蔽电极和终端结构的终端电极被配置为接收栅极电压。 图案化导电层被配置为分别通过第一接触插塞和第二接触插塞电接触所述栅电极和端接电极。
    • 5. 发明申请
    • POWER SEMICONDUCTOR DEVICE HAVING LOW ON-STATE RESISTANCE
    • 功率半导体器件具有低的状态电阻
    • US20160149034A1
    • 2016-05-26
    • US14555518
    • 2014-11-26
    • SINOPOWER SEMICONDUCTOR, INC.
    • PO-HSIEN LIGUO-LIANG YANG
    • H01L29/78H01L29/06H01L29/417H01L29/40H01L29/423
    • H01L29/7813H01L29/0634H01L29/1095H01L29/407H01L29/7397H01L29/7811
    • A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.
    • 具有低导通电阻的功率半导体器件包括其上形成有外延层的衬底,栅极结构,端接结构和图案化导电层。 外延层具有至少第一沟槽和第二沟槽。 栅极结构嵌入在第一沟槽中,包括设置在栅电极下方的栅电极和屏蔽电极。 端接结构嵌入在第二沟槽中,包括端接电极。 图案化的导电层设置在外延层的上方。 特别地,栅极结构的屏蔽电极和终端结构的终端电极被配置为接收栅极电压。 图案化导电层被配置为分别通过第一接触插塞和第二接触插塞电接触所述栅电极和端接电极。
    • 6. 发明授权
    • Trench power device and manufacturing method thereof
    • 沟槽动力装置及其制造方法
    • US08860134B1
    • 2014-10-14
    • US14016444
    • 2013-09-03
    • Sinopower Semiconductor, Inc.
    • Po-Hsien Li
    • H01L29/78
    • H01L29/7813H01L29/0638H01L29/0878H01L29/1095H01L29/407H01L29/41766H01L29/66727H01L29/66734H01L29/7811
    • A trench power device includes a semiconductor layer, a trench gate structure, a trench source structure, and a contact. The semiconductor layer has an epitaxial layer, a doped body region, a S/D region, and a doped contact-carrying region. The doped body region is formed in the epitaxial layer, the S/D region is formed in the doped body region, and the doped contact-carrying region is formed in the doped body region and outside a projecting portion defined by orthogonally projecting from the S/D region to the doped body region. The trench gate structure is embedded in the S/D region, the doped body region, and the epitaxial layer. The trench source structure is embedded in the doped body region and the epitaxial layer, and is connected to the doped contact-carrying region. The contact is connected to the S/D region and the doped contact-carrying region.
    • 沟槽功率器件包括半导体层,沟槽栅极结构,沟槽源结构和接触。 半导体层具有外延层,掺杂体区,S / D区和掺杂接触区。 掺杂体区域形成在外延层中,S / D区形成在掺杂体区域中,并且掺杂的接触区形成在掺杂体区域中,并且在从S的正交突出部限定的突出部分的外侧形成 / D区域。 沟槽栅极结构嵌入在S / D区域,掺杂体区域和外延层中。 沟槽源结构嵌入在掺杂体区域和外延层中,并连接到掺杂的接触区域。 该触点连接到S / D区和掺杂的接触区。