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    • 12. 发明授权
    • Method for producing a refractive or diffractive optical device
    • 屈光或衍射光学器件的制造方法
    • US09529127B2
    • 2016-12-27
    • US14352426
    • 2012-10-17
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Michel Heitzmann
    • G03F7/20G02B5/18G03F7/00B29D11/00G02B3/08G02B3/00
    • G02B5/1857B29D11/00769G02B3/08G02B5/1876G02B2003/0093G03F7/0005G03F7/0035G03F7/2002
    • A method producing a refractive or diffractive optical device, including: production, in a first layer, of at least one inclined general profile approximated by a staircase profile including plural stairsteps; production of the profile including: forming buffer patterns on the first layer and at least one sequence including: forming masking patterns, so each masking pattern includes at least one edge situated above a buffer pattern and covers at least one area of the first layer not masked by the buffer patterns, the forming the masking patterns also defining, for the first layer, plural free areas not masked by the masking patterns or by the buffer patterns; etching the free areas to form trenches in the first layer. The production of the profile also includes: removing the masking patterns, removing the buffer patterns revealing walls previously covered by the buffer patterns, and then an isotropic etching to remove the walls.
    • 一种产生折射或衍射光学装置的方法,包括:在第一层中生产由包括多个步骤的阶梯轮廓近似的至少一个倾斜的一般轮廓; 该简档的生成包括:在第一层上形成缓冲图案和至少一个序列,包括:形成掩模图案,因此每个掩模图案包括位于缓冲图案上方的至少一个边缘并且覆盖未被掩蔽的第一层的至少一个区域 通过缓冲器图案,形成掩蔽图案也为第一层限定未被掩蔽图案掩蔽的多个空闲区域或缓冲图案; 蚀刻自由区域以在第一层中形成沟槽。 轮廓的生产还包括:去除掩模图案,去除显示先前被缓冲图案覆盖的壁的缓冲图案,然后进行各向同性蚀刻以去除壁。
    • 13. 发明授权
    • Method for producing a microelectronic device
    • 微电子器件的制造方法
    • US09521794B2
    • 2016-12-13
    • US14193291
    • 2014-02-28
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Henri Sibuet
    • H05K3/02H05K3/10H05K13/04H01L49/02H01L23/522H01L27/02
    • H05K13/046H01L23/5223H01L27/0203H01L28/91H01L2924/0002H01L2924/00
    • A method for producing a microelectronic device including a substrate and a stack having at least one electrically conductive layer and at least one dielectric layer. The method includes formation, from one face of the substrate, of at least one pattern that is in depression with respect to a plane of the face of the substrate, the wall of the pattern having a bottom part and a flank part, the flank part being situated between the bottom part and the face of the substrate, the flank part having at least one inclined wall as far as the face of the substrate. With formation of the stack, the layers of the stack helping at least partially fill in the pattern. The stack is thinned of the stack at least as far as the plane of the face of the substrate so as to completely expose the edge of said at least one electrically conductive layer flush in one plane, and at least one electrical connection member is formed on the substrate in contact with the edge of the at least one electrically conductive layer.
    • 一种用于制造包括具有至少一个导电层和至少一个电介质层的衬底和堆叠的微电子器件的方法。 该方法包括从衬底的一个表面形成至少一个相对于衬底的表面的平面处于凹陷中的图案,图案的壁具有底部和侧面部分,侧面部分 位于基底的底部和表面之间,所述侧面部分具有至少一个倾斜的壁至基底的表面。 随着堆叠的形成,堆叠的层有助于至少部分地填充图案。 叠层至少与衬底表面的平面变薄,从而将所述至少一个导电层的边缘完全暴露在一个平面中,并且至少一个电连接构件形成在 所述基板与所述至少一个导电层的边缘接触。
    • 14. 发明授权
    • Optical network and data processing system comprising such an optical network
    • 包括这种光网络的光网络和数据处理系统
    • US09479256B2
    • 2016-10-25
    • US14547511
    • 2014-11-19
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Yvain Thonnart
    • H04B10/27G02B6/43H04B10/80
    • H04B10/27G02B6/43H04B10/801
    • An optical network including: a medium; at least one beam of optical waveguides extending over the medium; for each beam, interfaces between the beam and the processing units, respectively. The beam successively links the interfaces in a closed loop oriented in a certain direction of rotation of information. The communication units of each interface are transversely arranged in ranks increasing from the periphery to the interior of the beam. First and second optical waveguides start from different interfaces or end at different interfaces. The first optical waveguide links two communication units both of them readers and/or writers of different ranks in first and second respective interfaces. The second optical waveguide passes through a communication unit from the second interface of lower rank to that of the communication unit of said second interface through which the first optical waveguide passes.
    • 一种光网络,包括:介质; 在介质上延伸的至少一束光波导; 对于每个光束,分别在光束和处理单元之间的接口。 光束在面向信息的某个旋转方向的闭环中连续地连接接口。 每个界面的通信单元横向布置成从梁的周边到内部增加的等级。 第一和第二光波导从不同的接口开始或在不同的接口处结束。 第一光波导将第一和第二相应接口中的读取器和/或不同等级的写入器的两个通信单元连接起来。 第二光波导通过通信单元从下级的第二接口到第一光波导通过的所述第二接口的通信单元的通信单元。
    • 15. 发明授权
    • Method for depositing nanoparticles on a nanostructured metal oxide substrate
    • 在纳米结构金属氧化物衬底上沉积纳米颗粒的方法
    • US09393591B2
    • 2016-07-19
    • US14396948
    • 2013-04-23
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Dimitry AldakovValentina Ivanova-HristovaPeter ReissSylvia Sanchez
    • B05D1/36B05D3/00H01L51/00B05D1/38H01L51/42
    • B05D1/36B05D1/38B05D3/002H01L51/0003H01L51/4226H01L51/4233Y02E10/549
    • The present invention relates to a method for depositing nanoparticles (NPs) on a nanostructured metal oxide (NSMO) substrate, characterized in that it comprises the steps of: a) functionalizing the NSMO substrate with a bifunctional coupling agent carrying a first function, this first function being a phosphonic function that forms a bond with the NSMO, and a second function that is intended to form a bond with a nanoparticle; and b) grafting the nanoparticles via a bond with the second function of the coupling agent. The invention also relates to a stack comprising a nanostructured metal oxide substrate covered with nanoparticles by way of a bifunctional coupling agent carrying a first function, this first function being a phosphonic function and forming a bond with the NSMO, and a second function that is intended to form a bond with a nanoparticle.The invention is applicable to the field of microelectronics and especially to the production of electrodes and the production of photovoltaic panels.
    • 本发明涉及一种在纳米结构金属氧化物(NSMO)衬底上沉积纳米颗粒(NPs)的方法,其特征在于其包括以下步骤:a)用携带第一功能的双功能偶联剂对NSMO衬底进行官能化,该第一 功能是与NSMO形成键的膦酸官能团,以及旨在与纳米颗粒形成键的第二个功能; 和b)通过与偶联剂的第二功能的键接合纳米颗粒。 本发明还涉及一种包含纳米结构的金属氧化物衬底的叠层,该纳米结构金属氧化物衬底通过具有第一功能的双功能偶联剂覆盖纳米颗粒,该第一个功能是膦酸化功能并与NSMO形成键,以及预期的第二个功能 以形成与纳米颗粒的键。 本发明适用于微电子领域,特别适用于生产电极和生产光电板。
    • 16. 发明授权
    • Method for manufacturing a microelectronic device including depositing identical or different metallic layers on the same wafer
    • 用于制造微电子器件的方法,包括在同一晶片上沉积相同或不同的金属层
    • US09379024B2
    • 2016-06-28
    • US14591273
    • 2015-01-07
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Claire FournierFrederic-Xavier GaillardFabrice Nemouchi
    • H01L21/8238
    • H01L21/823821H01L21/823807H01L21/823814
    • A method for manufacturing a microelectronic device is provided, including forming a first semiconductor material layer on a first region of a top surface of a substrate; and forming a second semiconductor material layer on a second region of the top surface of the substrate distinct from the first region, forming a first metallic layer above the first layer; forming a first contact layer of a first intermetallic compound or solid solution; forming a first sacrificial layer in an upper portion of the first contact layer; forming a second sacrificial layer in an upper portion of the second layer; removing all of the second sacrificial layer so as to expose a residual portion of the second layer; partially removing the first sacrificial layer; forming a second metallic layer above said residual portion; and forming a second contact layer of a second intermetallic compound or solid solution.
    • 提供了一种用于制造微电子器件的方法,包括在衬底的顶表面的第一区域上形成第一半导体材料层; 以及在所述基板的顶表面的与所述第一区域不同的第二区域上形成第二半导体材料层,在所述第一层上方形成第一金属层; 形成第一金属间化合物或固溶体的第一接触层; 在所述第一接触层的上部形成第一牺牲层; 在所述第二层的上部形成第二牺牲层; 去除所有第二牺牲层以露出第二层的残留部分; 部分地去除第一牺牲层; 在所述残留部分上方形成第二金属层; 以及形成第二金属间化合物或固溶体的第二接触层。
    • 20. 发明授权
    • Low consumption logic circuit with mechanical switches
    • 低功耗逻辑电路,带机械开关
    • US09257981B2
    • 2016-02-09
    • US14452698
    • 2014-08-06
    • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    • Herve FanetMarc Belleville
    • H03K19/00B81B7/02
    • H03K19/0019B81B7/02B81B2201/01
    • Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronization input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronization input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronization input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronization input and between the second output and the supply and synchronization input.
    • 具有第一和第二输入的绝热逻辑电路,第一和第二输出以及至少一个电源和同步输入(Phi),该电路包括:第一逻辑器件,包括至少一个第一微机电和/或纳米机电开关, 被称为第一机械开关,由第一输入端控制并连接到第一输出端和供电和同步输入端;与第一逻辑器件相对的第二逻辑器件,包括至少一个第二微机电或纳米机电开关,称为第二机械 开关,由第二输入端控制并连接到第二输出端和供电和同步输入端,用于部分放电的第一和第二器件分别连接在第一输出与电源同步输入之间以及第二输出与供电和同步之间 输入。