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    • 13. 发明申请
    • SYSTEMS AND METHODS FOR DYNAMIC RANGE ENHANCEMENT USING AN OPEN-LOOP MODULATOR IN PARALLEL WITH A CLOSED-LOOP MODULATOR
    • 使用闭环调制器与闭环调制器并联的动态范围增强的系统和方法
    • US20170047895A1
    • 2017-02-16
    • US15336995
    • 2016-10-28
    • Cirrus Logic, Inc.
    • Ramin ZANBAGHI
    • H03F1/02H03F3/185H03F3/217H03F1/30
    • An integrated circuit may have two signal paths: an open-loop modulator (which may comprise a digital-input Class-D amplifier) and a closed-loop modulator (which may comprise an analog-input Class-D amplifier). A control subsystem may be capable of selecting either of the open-loop modulator or the closed-loop modulator as a selected path based on one or more characteristics (e.g., signal magnitude) of an input audio signal. For example, for higher-magnitude signals, the closed-loop modulator may be selected while the open-loop modulator may be selected for lower-magnitude signals. In some instances, when the open-loop modulator is selected as the selected path, the closed-loop modulator may power off, which may reduce power consumption. In addition, one or more techniques may be applied to reduce or eliminate user-perceptible audio artifacts caused by switching between the open-loop modulator and the closed-loop modulator, and vice versa.
    • 集成电路可以具有两个信号路径:开环调制器(其可以包括数字输入D类放大器)和闭环调制器(其可以包括模拟输入D类放大器)。 控制子系统可以基于输入音频信号的一个或多个特性(例如,信号幅度)来选择开环调制器或闭环调制器中的任一个作为选择的路径。 例如,对于较高幅度的信号,可以选择闭环调制器,同时为低电平信号选择开环调制器。 在一些情况下,当选择开环调制器作为选择的路径时,闭环调制器可以断电,这可能降低功耗。 此外,可以应用一种或多种技术来减少或消除由开环调制器和闭环调制器之间的切换引起的用户可感知的音频伪像,反之亦然。
    • 17. 发明授权
    • Beamforming a digital microphone array on a common platform
    • 在一个通用平台上成像一个数字麦克风阵列
    • US09467778B2
    • 2016-10-11
    • US13844802
    • 2013-03-16
    • Cirrus Logic, Inc.
    • Eric J. SwansonEd Schneider
    • H04R3/00
    • H04R3/005
    • An interface for an array of digital microphones in an electronic device may include a head-end chip coupled to the digital microphones through a bus. The bus may be shared by each microphone of the array of microphones and be multiplexed to allow transmission of data from the microphones to the head-end chip and transmission of power from the head-end chip to the array of digital microphones. The head-end chip may perform signal processing on receive data from the array of digital microphones to create beamforming arrays. The array of microphones may include microphones with different characteristics to improve performance of the array of microphones.
    • 用于电子设备中的数字麦克风阵列的接口可以包括通过总线耦合到数字麦克风的头端芯片。 总线可以由麦克风阵列的每个麦克风共享,并被复用以允许数据从麦克风传输到头端芯片,并将功率从头端芯片传输到数字麦克风阵列。 前端芯片可以对来自数字麦克风阵列的接收数据执行信号处理,以创建波束成形阵列。 麦克风阵列可以包括具有不同特性的麦克风,以改善麦克风阵列的性能。
    • 20. 发明申请
    • FULLY DEPLETED REGION FOR REDUCED PARASITIC CAPACITANCE BETWEEN A POLY-SILICON LAYER AND A SUBSTRATE REGION
    • 完全覆盖的区域,用于降低聚硅层和基片区域之间的平行电容
    • US20160145093A1
    • 2016-05-26
    • US14942824
    • 2015-11-16
    • Cirrus Logic, Inc.
    • Shanjen PanMarc L. Tarabbia
    • B81B3/00B81C1/00H04R23/00
    • B81B3/0086B81B2201/0257B81C1/00698H04R19/005H04R19/04H04R2307/025
    • A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.
    • 可以使用完全耗尽区域来减少具有多晶硅层的电子器件中的多对衬底寄生电容。 当完全耗尽区域至少部分地位于电子器件下方时,在完全耗尽区域和衬底区域之间形成附加的寄生电容。 该额外的寄生电容与电子器件的多晶硅层与掺杂区域之间的第一寄生电容串联耦合。 第一寄生电容和附加寄生电容的串联组合导致电子器件的寄生电容体验的总体减小。 该结构可以在电子器件的侧面上包括两个掺杂区域,以基于掺杂区域和衬底区域中掺杂剂的横向相互作用形成完全耗尽区域。