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11. 发明授权

US08423873B2 Decoding techniques for correcting errors using soft information 有权
标题翻译：使用软信息纠正错误的解码技术
公开(公告)号：US08423873B2
公开(公告)日：2013-04-16
申请号：US12787120
申请日：2010-05-25
申请人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
发明人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
IPC分类号： H03M13/00
CPC分类号： H03M13/45 , G11B20/1833 , G11B2020/1863 , G11B2220/2516 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/2906 , H03M13/2909 , H03M13/2945 , H03M13/2957 , H03M13/3784 , H03M13/4146 , H03M13/6343
摘要： Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
摘要翻译：使用第一和第二级解码器执行两级纠错解码。可以使用通过组合内部组件代码和外部组件代码形成的组合代码来解码数据并纠正任何错误。使用复合代码执行两级解码允许内部奇偶校验块的大小减少到单个Reed-Solomon符号，同时保持良好的代码率。第一级解码器产生软信息。软信息可以指示内部组件代码的每个可能的综合征值的最可能的错误事件。软信息还可以包括每个最可能的错误事件的误差度量值。第二级解码器使用外部分量代码基于软信息生成校正的校正子值。然后选择对应于校正的综合征值的最可能的网格路径。

12. 发明授权

US08209578B2 Systems using low density parity check codes for correcting errors 有权
标题翻译：使用低密度奇偶校验码纠正错误的系统
公开(公告)号：US08209578B2
公开(公告)日：2012-06-26
申请号：US12046108
申请日：2008-03-11
申请人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
发明人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
IPC分类号： H03M13/05
CPC分类号： H03M13/1111 , G11B20/18
摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.
摘要翻译：系统校正位流中的错误。该系统包括编码器和解码器。编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。

13. 发明授权

US08037394B2 Techniques for generating bit reliability information in a post-processor using an error correction constraint 有权
标题翻译：使用纠错约束在后处理器中生成比特可靠性信息的技术
公开(公告)号：US08037394B2
公开(公告)日：2011-10-11
申请号：US11771783
申请日：2007-06-29
申请人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
发明人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
IPC分类号： H03M13/45
CPC分类号： G11B20/1833 , G11B20/10046 , G11B2020/185 , G11B2020/1863 , H03M13/1102 , H03M13/2957 , H03M13/6343
摘要： Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
摘要翻译：提供了为检测到的序列生成位可靠性的技术。检测器产生检测到的序列。根据一个实施例，后处理器在检测到的序列中找到一个或多个错误事件的组合的第一组，其满足对应于第一位值的完整集合或纠错约束的子集，找到第二组组合检测到的序列中的一个或多个错误事件满足对应于第二位值的完整集合或纠错约束的子集，选择第一集合中的一个或多个事件的第一最有可能的组合和第一集合的第二最有可能的组合或更多的事件，并且基于第一和第二最有可能的值产生位可靠性。

14. 发明授权

US08037393B2 Techniques for generating bit reliability information in the post processor 有权
标题翻译：用于在后处理器中生成位可靠性信息的技术
公开(公告)号：US08037393B2
公开(公告)日：2011-10-11
申请号：US11771226
申请日：2007-06-29
申请人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
发明人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
IPC分类号： H03M13/45
CPC分类号： H03M13/45 , H03M13/11 , H03M13/41 , H03M13/43 , H03M13/6575 , H04L1/005
摘要： A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
摘要翻译：检测器产生检测到的序列，并且后处理器产生指示检测到的序列中的多个错误事件的可能性的概率值。后处理器将值分为第一和第二子集。后处理器从值的第一子集中选择第一最可能的值，并从值的第二子集中选择第二最有可能的值。后处理器基于第一和第二最可能的值产生位可靠性。

15. 发明授权

US07590920B2 Reduced complexity error correction encoding techniques 有权
标题翻译：降低复杂度纠错编码技术
公开(公告)号：US07590920B2
公开(公告)日：2009-09-15
申请号：US11198943
申请日：2005-08-05
申请人： Shaohua Yang , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi
发明人： Shaohua Yang , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi
IPC分类号： H03M13/00
CPC分类号： H03M13/29 , H03M13/1515 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.
摘要翻译：纠错编码器将冗余奇偶校验信息插入到数据流中，以提高系统的可靠性。编码器可以使用复合代码生成冗余奇偶校验信息。在由后续编码生成的奇偶校验信息保留的位置中将虚拟位插入到数据流中。纠错码可以具有均匀或不均匀的间距。该跨度对应于用于形成复合代码的较小奇偶码的单个块内的连续通道位。跨越整个码字的跨度长度可以通过在少于所有跨度的位置插入虚拟位而变化。

16. 发明授权

US07142134B2 Techniques for generating modulation codes using running substitutions 有权
公开(公告)号：US07142134B2
公开(公告)日：2006-11-28
申请号：US11049554
申请日：2005-02-01
申请人： Mario Blaum , Ksenija Lakovic , Bruce A. Wilson
发明人： Mario Blaum , Ksenija Lakovic , Bruce A. Wilson
IPC分类号： H03M7/00 , H03M13/21
CPC分类号： H03M5/145
摘要： Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.

17. 发明授权

US07126502B2 Techniques for using interleaved encoders to obtain modulation constraints 有权
公开(公告)号：US07126502B2
公开(公告)日：2006-10-24
申请号：US11049403
申请日：2005-02-01
申请人： Mario Blaum , Ksenija Lakovic , Bruce A. Wilson
发明人： Mario Blaum , Ksenija Lakovic , Bruce A. Wilson
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426
摘要： Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

18. 发明申请

US20060170578A1 Techniques for generating modulation codes using running substitutions 有权
标题翻译：使用运行替换产生调制码的技术
公开(公告)号：US20060170578A1
公开(公告)日：2006-08-03
申请号：US11049554
申请日：2005-02-01
申请人： Mario Blaum , Ksenija Lakovic , Bruce Wilson
发明人： Mario Blaum , Ksenija Lakovic , Bruce Wilson
IPC分类号： H03M3/00
CPC分类号： H03M5/145
摘要： Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.
摘要翻译：提供了用于执行已知导致错误的比特序列的替换的技术。输入数据最初被调制编码。然后在滑动窗口中分析调制的数据，以确定其是否包含已知导致错误的任何附加位序列。如果在数据中识别出易出错位序列，则替换引擎以预定的不太可能引起错误的比特位替换易错位序列。然后将替代引擎的比特流输出记录在存储介质上。记录的比特流在从介质读取时被解码。解码过程识别取代的位模式，并用原始的位序替换替换的模式。

19. 发明申请

US20100172048A1 Servo patterns for patterned media 失效
标题翻译：图案媒体的伺服图案
公开(公告)号：US20100172048A1
公开(公告)日：2010-07-08
申请号：US12661390
申请日：2010-03-15
申请人： Thomas Robert Albrecht , Mario Blaum , Ksenija Lakovic , Bruce Alexander Wilson , Satoshi Yamamoto
发明人： Thomas Robert Albrecht , Mario Blaum , Ksenija Lakovic , Bruce Alexander Wilson , Satoshi Yamamoto
IPC分类号： G11B20/14 , G11B5/09
CPC分类号： G11B5/855 , B82Y10/00 , G11B5/59655 , G11B5/743 , G11B20/1403 , G11B20/1426 , G11B2020/1281 , G11B2020/1484 , G11B2220/2516
摘要： Servo patterns for patterned media. The servo pattern includes specification of cylinder/track ID with and without a Gray code. The servo pattern space is minimized by the optimum usage of the islands. This is achieved by island allocation rules to take advantage of non-magnetic island. The island allocation also provides for easier lift-off. Logic is used to encode and decode the Gray code. Further, the Gray code is designed to stabilize the magnetic island/non-magnetic island ratio to allow for easier manufacture.
摘要翻译：图案媒体的伺服图案。伺服模式包括具有和不具有格雷码的气缸/轨道ID的规格。通过岛的最佳使用使伺服图案空间最小化。这是通过岛屿分配规则实现的，以利用非磁性岛屿。岛屿分配也提供了更轻松的起飞。逻辑用于对格雷码进行编码和解码。此外，格雷码被设计为稳定磁岛/非磁岛比，以便于制造更容易。

20. 发明授权

US07725800B2 Decoding techniques for correcting errors using soft information 有权
标题翻译：使用软信息纠正错误的解码技术
公开(公告)号：US07725800B2
公开(公告)日：2010-05-25
申请号：US11198945
申请日：2005-08-05
申请人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
发明人： Shaohua Yang , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Travis Oenning , Jongseung Park , Hideki Sawaguchi , Bruce A. Wilson
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H03M13/45 , G11B20/1833 , G11B2020/1863 , G11B2220/2516 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/2906 , H03M13/2909 , H03M13/2945 , H03M13/2957 , H03M13/3784 , H03M13/4146 , H03M13/6343
摘要： Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
摘要翻译：使用第一和第二级解码器执行两级纠错解码。可以使用通过组合内部组件代码和外部组件代码形成的组合代码来解码数据并纠正任何错误。使用复合代码执行两级解码允许内部奇偶校验块的大小减少到单个Reed-Solomon符号，同时保持良好的代码率。第一级解码器产生软信息。软信息可以指示内部组件代码的每个可能的综合征值的最可能的错误事件。软信息还可以包括每个最可能的错误事件的误差度量值。第二级解码器使用外部分量代码基于软信息生成校正的校正子值。然后选择对应于校正的综合征值的最可能的网格路径。

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