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11. 发明授权

US5055802A Multiaccumulator sigma-delta fractional-N synthesis 失效
$Multiaccumulator sigma-delta fractional-N synthesis$
标题翻译：多功能分子SIGMA-DELTA分数合成
公开(公告)号：US5055802A
公开(公告)日：1991-10-08
申请号：US516993
申请日：1990-04-30
申请人： Alexander W. Hietala , Duane C. Rabe
发明人： Alexander W. Hietala , Duane C. Rabe
IPC分类号： H03C3/09 , H03L7/197 , H03M3/00 , H03M7/32
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1976
摘要： A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
摘要翻译：公开了采用至少二阶Σ-Δ调制器的分数N合成器。来自Σ-Δ调制器的输出累加器的最高有效位用作循环分频器的可变因数的进位控制。引入到合成器的调制作为Σ-Δ调制器的数字数字输入的一部分，并且通过选择大数作为循环除数除数的分数部分的分母来减少寄生信号输出。

12. 发明授权

US4851798A Unitary tuning structure 失效
标题翻译：单一调谐结构
公开(公告)号：US4851798A
公开(公告)日：1989-07-25
申请号：US175898
申请日：1988-03-31
申请人： Alexander W. Hietala , Max W. Muterspaugh
发明人： Alexander W. Hietala , Max W. Muterspaugh
IPC分类号： H03J1/00 , H03J3/18 , H05K1/02 , H05K1/18
CPC分类号： H03J3/185 , H05K1/0237 , H05K1/18
摘要： A unitary tuning structure of a UHF tuner includes an inductance loop, an inductance adjustment element attached to a top portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis parallel to the printed circuit board to which the inductance loop is attached and a capacitance adjustment tab attached to a side portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis perpendicular to the printed circuit board. In another form of the unitary tuning structure, a second inductance loop can be attached within the first loop.

13. 发明授权

US5495206A Fractional N frequency synthesis with residual error correction and method thereof 失效
标题翻译：具有残余误差校正的分数N频率合成及其方法
公开(公告)号：US5495206A
公开(公告)日：1996-02-27
申请号：US146257
申请日：1993-10-29
申请人： Alexander W. Hietala
发明人： Alexander W. Hietala
IPC分类号： H03L7/18 , H03C3/09 , H03L7/089 , H03L7/197
CPC分类号： H03L7/0898 , H03L7/1976
摘要： A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).
摘要翻译：频率合成器（107）利用其输出用作频率合成器输出（115）的可变振荡器（114），并被馈送到数字分频器（108）。数字分频器（108）的输出馈送相位比较器（109）的一个输入端。相位比较器（109）的另一个输入端从参考振荡器（116）馈送。相位比较器（109）输出控制可变振荡器（114）。数字分频器（108）具有通过多累加器分数N分频系统（112）随时间变化的分频比，使得有效分频比可以通过非整数步长而变化。由于施加到数字分频器（108）的时变分割序列在输出信号（115）上存在残留杂散电平。来自多个累加器分数的第二个数字序列。产生N分系统（112）以减小该杂散电平并将其施加到相位比较器（109）的输出。

14. 发明授权

US5424689A Filtering device for use in a phase locked loop controller 失效
标题翻译：用于锁相环控制器的滤波装置
公开(公告)号：US5424689A
公开(公告)日：1995-06-13
申请号：US172000
申请日：1993-12-22
申请人： Steven F. Gillig , Alexander W. Hietala
发明人： Steven F. Gillig , Alexander W. Hietala
IPC分类号： H03L7/089 , H03L7/107 , H03L7/093
CPC分类号： H03L7/107 , H03L7/0893
摘要： A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.
摘要翻译：在无线电话机中使用锁相环（PLL）频率合成器来向发射机或接收机提供参考频率。该特定PLL频率合成器具有宽带控制环路，具有高电流电荷泵（417）和具有低电流电荷泵（411）的窄带宽控制回路。在相位检测器（405）的输出处使用死区电路（413）来控制向高电流电荷泵（417）施加误差信号。此外，PLL频率合成器利用环路滤波器（419）。环路滤波器（419）接收两个校正信号（409'，415'），并为VCO（压控振荡器）（423）提供单个控制信号。环路滤波器包含由电阻和电容元件形成的两个时间常数。两个时间常数控制两个控制回路的带宽。

15. 发明授权

US5093632A Latched accumulator fractional N synthesis with residual error reduction 失效
$Latched accumulator fractional N synthesis with residual error reduction$
标题翻译：具有残余误差的锁定累加器分数N合成
公开(公告)号：US5093632A
公开(公告)日：1992-03-03
申请号：US576333
申请日：1990-08-31
申请人： Alexander W. Hietala , Duane C. Rabe
发明人： Alexander W. Hietala , Duane C. Rabe
IPC分类号： H03L7/183 , H03L7/197
CPC分类号： H03L7/1976
摘要： A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).
摘要翻译：公开了一种用于数字无线电转接器的具有减小的残余误差的锁存的累加器分数N合成器。合成器的分频器（103）的除数随时间通过累加器进位输出数字序列的总和而变化，这导致频率增量等于参考频率的一部分。累加器（615,617）被锁存，使得在发生时钟脉冲时，数据通过每个累加器一次一个时钟脉冲步进传送，使得通过系统的延迟等于仅一个累加器的延迟。从最高阶累加器（621）的锁存输出中减去第二高阶累加器（619）的锁存输出，并在施加到环路滤波器（109）之前进行微分。

16. 发明授权

US5055803A Parameter tolerant PLL synthesizer 失效
标题翻译：参数容限PLL合成器
公开(公告)号：US5055803A
公开(公告)日：1991-10-08
申请号：US628533
申请日：1990-12-14
申请人： Alexander W. Hietala
发明人： Alexander W. Hietala
IPC分类号： H03L7/089 , H03L7/093 , H03L7/18
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/093
摘要： In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.
摘要翻译：在PLL合成器中，当环路的增益提高到初始设计的环路增益并且三阶环路对称比值减小到2.0范围内的值时，增益和分量变化的公差将大大降低到2.5。基于三阶对称比率范围的高阶环路具有相应较低的发射极频率以打开单位增益频率比。

17. 发明授权

US5055800A Fractional N/M synthesis 失效
标题翻译：部分N / M合成
公开(公告)号：US5055800A
公开(公告)日：1991-10-08
申请号：US516897
申请日：1990-04-30
申请人： Gregory Black , Alexander W. Hietala
发明人： Gregory Black , Alexander W. Hietala
IPC分类号： H03L7/183 , H03L7/187 , H03L7/197 , H03L7/20 , H04B1/38
CPC分类号： H03L7/183 , H03L7/1976 , H03L7/20 , H03L2207/10
摘要： A frequency synthesizer having a frequency divider and a frequency multiplier in the feedback loop is disclosed. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider, which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.
摘要翻译：公开了一种在反馈回路中具有分频器和倍频器的频率合成器。两个相邻合成信道之间的最小频率间隔等于参考频率除以乘法器的乘法比。可以分析为整数和小数部分之和的分频器的分频比随时间随数字序列而变化，导致等于参考频率的一小部分的最小频率增量。当分频比的分数部分通过降低环路的有效分频比而导致瞬时分频比的大变化时，乘法器用于降低频率合成器的非线性。

18. 发明授权

US4921465A Varactor tuned UHF RF signal input circuit 失效
标题翻译：变频器调谐UHF射频信号输入电路
公开(公告)号：US4921465A
公开(公告)日：1990-05-01
申请号：US175832
申请日：1988-03-31
申请人： Alexander W. Hietala , Max W. Muterspaugh
发明人： Alexander W. Hietala , Max W. Muterspaugh
IPC分类号： H03K5/02 , H03J3/02 , H03J3/18 , H04B1/08 , H04B1/18
CPC分类号： H03J3/185
摘要： An RF signal input circuit for a UHF tuner of a television receiver comprises a series-tuned circuit including a varactor diode and an inductance element connected in series, in the order named, between signal ground and a gate electrode of a field-effect transistor RF amplifier. The series-tuned circuit has a relatively uniform bandwidth throughout the UHF range. A capacitor connected in shunt with the gate electrode completes a "split-capacitor" configuration in which the varactor diode and the shunt capacitor form a variable impedance transformation network for making the relationship between the effective impedances of the series-tuned circuit and FET amplifier relatively uniform throughout the UHF range. The order of the varactor diode and inductance element allows a low cost adjustable capacitor comprising a grounded shield wall as one plate and a movable tab as a second plate to be connected directly across the varactor diode.

19. 发明授权

US06850574B2 Multiple bandwidth amplifier control systems for mobile stations and methods therefor 有权
标题翻译：用于移动台的多带宽放大器控制系统及其方法
公开(公告)号：US06850574B2
公开(公告)日：2005-02-01
申请号：US09854858
申请日：2001-05-14
申请人： Dale G. Schwent , Alexander W. Hietala
发明人： Dale G. Schwent , Alexander W. Hietala
IPC分类号： H03F3/189 , H03G1/00 , H03G3/20 , H03G3/30 , H04B1/04 , H04L27/20 , H04L27/36 , H04L25/03
CPC分类号： H03G3/3047 , H03G1/0088
摘要： RF amplifier control circuits for transmitters in mobile communication devices, combinations thereof and methods therefor. The control circuits include generally proportional and integral control circuits having an output coupled to a control input of an amplifier. An initial control signal is applied to the amplifier before a vector modulator output coupled an input thereof is at full output power. The vector modulator output is ramped to full output after applying the initial control signal. Thereafter, the initial control signal applied to the amplifier during ramping is corrected by integrating an output of the amplifier relative to a second reference signal with an integral control circuit coupled to the control input of the amplifier, the second reference signal is proportional to the ramping vector modulator output.
摘要翻译：用于移动通信设备中的发射机的RF放大器控制电路，其组合及其方法。控制电路包括具有耦合到放大器的控制输入端的输出的通常成比例且整体的控制电路。在耦合其输入的矢量调制器输出处于全输出功率之前，将初始控制信号施加到放大器。施加初始控制信号后，向量调制器输出斜坡变为全输出。此后，通过将放大器的输出相对于第二参考信号与放大器的控制输入耦合的积分控制电路进行积分来校正在斜坡期间施加到放大器的初始控制信号，第二参考信号与斜坡成比例矢量调制器输出。

20. 发明授权

US06327319B1 Phase detector with frequency steering 有权
标题翻译：频率转向相位检测器
公开(公告)号：US06327319B1
公开(公告)日：2001-12-04
申请号：US09187621
申请日：1998-11-06
申请人： Alexander W. Hietala , David M. Gonzalez
发明人： Alexander W. Hietala , David M. Gonzalez
IPC分类号： H03D324
CPC分类号： H03L7/141 , H03L7/0891 , H03L7/18
摘要： A PLL (225) includes a phase detector (202) and a charge pump (210 or 212). The phase detector (202) includes a first D-type flip flop (302), a second D-type flip flop (304) and an AND gate forming a reset circuit (306). The charge pump (210 or 212) includes an up current source (308) and a down current source (310). The up current source (308) provides a constant current. The down current source (310) varies responsive to an output signal (207) generated by the second D-type flip flop (304). The constant current provided by the up current source (308) is made to be less than one half the current provided by the down current source (310) to bias the charge pump (210 or 212) in a negative direction to minimize false locks between the phase of a divided reference frequency signal (206) and the phase of a divided voltage controlled oscillator frequency signal (209). Alternatively, the up current source (308) may be controlled in an analogous manner with the down current source (310) being held constant to achieve a similar effect and advantage.
摘要翻译： PLL（225）包括相位检测器（202）和电荷泵（210或212）。相位检测器（202）包括第一D型触发器（302），第二D型触发器（304）和形成复位电路（306）的与门。电荷泵（210或212）包括上升电流源（308）和下降电流源（310）。上电流源（308）提供恒定电流。响应于由第二D型触发器（304）产生的输出信号（207），下降电流源（310）变化。由上升电流源（308）提供的恒定电流被设定为小于由下降电流源（310）提供的电流的一半，以使电荷泵（210或212）在负方向上偏置，以最小化在分频参考频率信号（206）的相位和分压电压振荡器频率信号（209）的相位。或者，上电流源（308）可以以类似的方式被控制，使得下降电流源（310）保持恒定以获得类似的效果和优点。

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