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1. 发明申请

US20180191360A1 TUNED OFFSET PHASE-LOCKED LOOP TRANSMITTER 审中-公开
公开(公告)号：US20180191360A1
公开(公告)日：2018-07-05
申请号：US15739690
申请日：2015-06-26
申请人： Olympus Corporation
发明人： John B. Groe , Kishore RAMA RAO
IPC分类号： H03L7/099 , H03B5/12 , H03C3/09
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03C3/0966 , H03C3/0983 , H03L2207/10 , H03L2207/12
摘要： Systems and methods are provided in which an offset phase-locked loop (PLL) system can be configured as part of a radio frequency transmitter. The PLL can include a phase detection circuit including a first input configured to receive an information signal and a second input configured to receive a feedback signal; a charge pump including an input coupled to the phase detection circuit and an output; a filter including an input coupled to the output of the charge pump; a voltage-controlled oscillator coupled to the charge pump and including an LC tank circuit comprising an inductive element and a capacitive element, wherein the inductive element of the LC tank circuit comprises the antenna; and a feedback path.

2. 发明申请

US20160105191A1 FREQUENCY SYNTHESIZER 审中-公开
标题翻译：频率合成器
公开(公告)号：US20160105191A1
公开(公告)日：2016-04-14
申请号：US14782921
申请日：2014-04-03
申请人： ZAKRYTOE AKCIONERNO OBSHHESTVO "NAYCHNO- PROIZVODSTVENNAYA FIRMA "MICRAN"
发明人： Andrei Viktorovich GOREVOI
IPC分类号： H03L7/18
CPC分类号： H03L7/18 , H03L7/185 , H03L2207/10
摘要： The output of a reference frequency generator is connected to the input of a high-order frequency multiplier, the output of which is connected to the input of an additional frequency multiplier and to a first input of a frequency converter. The output of the additional frequency multiplier is connected to the input of a frequency divider, the output of which is connected to a reference input of a frequency-phase detector. The output of the frequency converter is connected to the input of a frequency divider with a variable division ratio, the output of which is connected to another input of the frequency-phase detector. The output of the frequency-phase detector is connected to an error signal filter, the output of which is connected to the input of a controlled generator. A second input of the frequency converter is connected to the output of the controlled generator. The main technical result is an increase in the frequency resolution and spectral purity of an output signal.
摘要翻译：参考频率发生器的输出连接到高阶倍频器的输入，高频倍频器的输出连接到附加倍频器的输入端和变频器的第一输入端。附加倍频器的输出连接到分频器的输入，分频器的输出连接到频率相位检测器的参考输入。变频器的输出端连接到分频器的输入端，该分频器的输出分频比与频率相位检测器的另一个输入端相连。频率相位检测器的输出连接到误差信号滤波器，其输出端连接到受控发生器的输入端。变频器的第二输入端连接到受控发电机的输出端。主要的技术结果是增加了输出信号的频率分辨率和光谱纯度。

3. 发明授权

US09166606B2 Reference-frequency-insensitive phase locked loop 有权
标题翻译：参考频率不敏感的锁相环
公开(公告)号：US09166606B2
公开(公告)日：2015-10-20
申请号：US14452204
申请日：2014-08-05
申请人： MaxLinear, Inc.
发明人： Sheng Ye
IPC分类号： H03L7/08 , H03L7/085
CPC分类号： H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
摘要： A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
摘要翻译：锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。基于生成的参考时钟信号，锁相环可以使得能够使用晶体时钟信号的上升沿和下降沿。锁相环可以基于使能来执行锁相环的操作。基于晶体时钟信号的上升沿和下降沿，锁相环可执行相位比较功能。通过在锁相环中利用采样环路滤波器，锁相环可以在锁相环中的电荷泵的输出处消除与晶体时钟信号的占空比误差相关的干扰。

4. 发明授权

US08917124B1 Frequency multiplier jitter correction 有权
标题翻译：倍频器抖动校正
公开(公告)号：US08917124B1
公开(公告)日：2014-12-23
申请号：US14503656
申请日：2014-10-01
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03L7/06 , H03L7/091 , H03L7/093 , H03L7/097
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译：提供了一种用于倍频抖动校正的系统和方法。该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。使用压控振荡器（VCO）的PLL是倍频器的一个例子。该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。

5. 发明申请

US20100164561A1 SYSTEM AND METHOD FOR WIDEBAND PHASE-ADJUSTABLE COMMON EXCITATION 有权
标题翻译：用于宽带相位可调共享激励的系统和方法
公开(公告)号：US20100164561A1
公开(公告)日：2010-07-01
申请号：US12344961
申请日：2008-12-29
申请人： Jeff Roberg , Steve Jordan
发明人： Jeff Roberg , Steve Jordan
IPC分类号： H03B19/00
CPC分类号： H03L7/183 , H03L7/087 , H03L2207/10
摘要： A power generator system and apparatus that uses a frequency synthesizer in conjunction with an oscillator to lock both frequency of a drive signal with a reference signal. The oscillator center frequency is different from the nominal generator frequency, and as a consequence a variety of reference frequencies may be supported. By using a frequency synthesizer, the oscillator frequency can be locked onto a frequency that is a ratio of the reference frequency. Then, the frequency synthesizer may generate a drive signal that is closely matched to the reference frequency.
摘要翻译：一种发电机系统和装置，其使用与振荡器结合的频率合成器来锁定驱动信号的频率与参考信号。振荡器中心频率与标称发生器频率不同，因此可以支持多种参考频率。通过使用频率合成器，可以将振荡器频率锁定在作为参考频率的比率的频率上。然后，频率合成器可以产生与参考频率紧密匹配的驱动信号。

6. 发明授权

US07345515B2 Low power and low timing jitter phase-lock loop and method 失效
公开(公告)号：US07345515B2
公开(公告)日：2008-03-18
申请号：US11716485
申请日：2007-03-09
申请人： Dong Myung Choi
发明人： Dong Myung Choi
IPC分类号： H03L7/06
CPC分类号： G06F1/04 , G11C7/02 , G11C7/1006 , G11C7/1018 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/4093 , H03L7/0891 , H03L7/0995 , H03L7/16 , H03L2207/10
摘要： A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

7. 发明申请

US20060170469A1 Low power and low timing jitter phase-lock loop and method 失效
公开(公告)号：US20060170469A1
公开(公告)日：2006-08-03
申请号：US11394506
申请日：2006-03-31
申请人： Dong Choi
发明人： Dong Choi
IPC分类号： H03L7/06
CPC分类号： G06F1/04 , G11C7/02 , G11C7/1006 , G11C7/1018 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/4093 , H03L7/0891 , H03L7/0995 , H03L7/16 , H03L2207/10
摘要： A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

8. 发明授权

US07020230B2 Frequency synthesizer for dual mode receiver 有权
公开(公告)号：US07020230B2
公开(公告)日：2006-03-28
申请号：US10040534
申请日：2001-12-28
申请人： Nigel J. Tolson
发明人： Nigel J. Tolson
IPC分类号： H03D3/24 , H04B1/40 , H03K9/00
CPC分类号： H03J1/005 , H03L7/183 , H03L2207/10
摘要： In a portable dual mode receiver circuit, a dual modulus clock system is provided which can, by selective use of integer division on a multiplied master clock, select specific channels with two different channel spacings in several different bands, providing power and space savings and achieving simplicity of operation.

9. 发明授权

US06876261B2 Phase lock for synthesizer phase reference oscillator 失效
标题翻译：合成器相位基准振荡器的锁相
公开(公告)号：US06876261B2
公开(公告)日：2005-04-05
申请号：US10421236
申请日：2003-04-21
申请人： Linley F. Gumm
发明人： Linley F. Gumm
IPC分类号： H03L7/22 , H03L7/00
CPC分类号： H03L7/22 , H03L2207/10 , H03L2207/12
摘要： A phase lock for a synthesizer phase reference oscillator that is used in conjunction with a conventional DDS circuit to synthesize an RF output frequency includes a second DDS circuit that is added with a reference increment value as an input to provide a phase offset frequency. A frequency/phase comparator compares a frequency reference oscillator output with the phase offset frequency to generate a control signal for phase locking the phase reference oscillator to the frequency reference oscillator. To determine the correct value for the reference increment value, a switch is provided between the frequency/phase comparator and the phase reference oscillator and the control signal is input to an analog-to-digital converter. During a “turn on” procedure the resulting digitized control signal is observed by a control system as the reference increment value is adjusted until a slow ramp, positive or negative, in the control signal is observed. Then the switch is closed to allow the control signal to phase lock the phase reference oscillator coherently to the frequency reference oscillator. In this way coherence is achieved from unit to unit with a more precise frequency output.
摘要翻译：与常规DDS电路结合使用以合成RF输出频率的合成器相位基准振荡器的锁相包括添加有参考增量值作为输入以提供相位偏移频率的第二DDS电路。频率/相位比较器将频率参考振荡器输出与相位偏移频率进行比较，以产生用于将相位参考振荡器锁相到频率参考振荡器的控制信号。为了确定参考增量值的正确值，在频率/相位比较器和相位参考振荡器之间提供开关，并且控制信号被输入到模数转换器。在“打开”程序期间，由于控制系统观察到所得到的数字化控制信号，因为调整参考增量值，直到观察到控制信号中的缓慢斜坡正或负。然后开关闭合，以允许控制信号将相位参考振荡器相位锁定到频率参考振荡器。以这种方式，通过单位到单位实现更精确的频率输出的一致性。

10. 发明授权

US06720806B1 Method and circuit for producing a reference frequency signal using a reference frequency doubler having frequency selection controls 有权
标题翻译：使用具有频率选择控制的参考倍频器产生参考频率信号的方法和电路
公开(公告)号：US06720806B1
公开(公告)日：2004-04-13
申请号：US10132463
申请日：2002-04-25
申请人： Allen Carl Merrill , Joseph James Balardeta , Sudhaker Reddy Anumula
发明人： Allen Carl Merrill , Joseph James Balardeta , Sudhaker Reddy Anumula
IPC分类号： H03B1900
CPC分类号： H03L7/18 , H03K5/00006 , H03L2207/10
摘要： Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. The frequency doubler is provided with selection control for programming multiple frequencies.
摘要翻译：锁相环（PLL）的电路包括参考信号输入和倍频器。倍频器的输出是具有大约是初始参考信号的两倍的频率并被馈送到PLL的第二参考信号。倍频器包括具有耦合到倍频器的输入的输入的第一延迟电路; 以及具有耦合到延迟电路的输出的第一输入和耦合到倍频器的输入的第二输入的XOR电路。倍频器可以包括在第一延迟电路之后串联的一个或多个附加延迟电路，其输出被提供给多路复用器。多路复用器包括选择信号输入，用于选择要提供给异或电路的至少一个延迟电路的输出。倍频器允许PLL具有较小的反馈分频比和较高的环路增益，以减少抖动。倍频器具有用于编程多个频率的选择控制。

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