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11. 发明申请

US20080100345A1 Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays 有权
标题翻译：用于实现位于横杆阵列的纳米线交叉点处的自旋电子器件的逻辑门的方法和系统
公开(公告)号：US20080100345A1
公开(公告)日：2008-05-01
申请号：US11590959
申请日：2006-10-31
申请人： Alexandre M. Bratkovski , Wei Wu , Gregory S. Snider , R. Stanley Williams
发明人： Alexandre M. Bratkovski , Wei Wu , Gregory S. Snider , R. Stanley Williams
IPC分类号： H03K19/20
CPC分类号： H03K19/18 , B82Y10/00 , H01L27/22 , H03K3/45
摘要： Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.
摘要翻译：本发明的各种方法和系统实施例涉及使用位于纳米线交叉点处的自旋电子器件的纳米线交叉阵列来实现串行逻辑门。在本发明的一个实施例中，纳米线交叉串阵列包括第一纳米线和多个基本上平行的控制纳米线，所述纳米线被定位成使得每个对照纳米线与第一纳米线重叠。纳米线交叉开关阵列包括许多自旋电子器件。每个自旋电子设备被配置为将控制纳米线中的一个连接到第一纳米线并且用作用于控制控制纳米线和第一纳米线之间的信号传输的锁存器。

12. 发明授权

US07319416B2 Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays 失效
标题翻译：基于隧道电阻器结的微米级/纳米级解复用器阵列
公开(公告)号：US07319416B2
公开(公告)日：2008-01-15
申请号：US11343325
申请日：2006-01-30
申请人： Warren Robinett , Gregory S. Snider , Duncan Stewart , Joseph Straznicky
发明人： Warren Robinett , Gregory S. Snider , Duncan Stewart , Joseph Straznicky
IPC分类号： H03M7/14
CPC分类号： G11C8/10 , G11C13/0023 , H03M13/51
摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.
摘要翻译：本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址。编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位，代码字内部地址。编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联，代码字内部地址。

13. 发明授权

US07307448B2 Interconnectable nanoscale computational stages 有权
标题翻译：可互连的纳米级计算阶段
公开(公告)号：US07307448B2
公开(公告)日：2007-12-11
申请号：US11136935
申请日：2005-05-24
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/173
CPC分类号： H01L29/0665 , B82Y10/00 , H01L27/10 , H01L29/0673 , Y10S977/938
摘要： Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.
摘要翻译：本发明的实施例实现了包括多个可互连的纳米尺度计算阶段的计算电路。每个纳米尺度的计算阶段包括：（1）纳米尺度逻辑阵列; 和（2）与可配置逻辑阵列互连的多个纳米级闩锁阵列。每个纳米尺度的计算阶段接收信号并将信号传递通过纳米级逻辑阵列并传递到纳米尺度的锁存阵列。从纳米级锁存器阵列输出的信号可以被路由到另一个纳米尺度的计算阶段或者离开计算电路。

14. 发明授权

US06512188B2 Lockout mechanism for power tool 有权
公开(公告)号：US06512188B2
公开(公告)日：2003-01-28
申请号：US09949167
申请日：2001-09-07
申请人： David C. Campbell , Lynn E. Lentino , Gregory S. Snider , Harry R. Hall
发明人： David C. Campbell , Lynn E. Lentino , Gregory S. Snider , Harry R. Hall
IPC分类号： H01H920
CPC分类号： H01H13/08 , H01H3/20 , H01H9/06
摘要： A switch lockout mechanism for a power tool includes a handle housing for gripping by a power tool operator. The handle housing is generally elongated in a direction corresponding to the gripping axis of a power tool operator. A switch is attached to the housing and is actuatable between an “on” position and an “off” position. A locking member is rotatably or pivotally attached to the housing. The locking member is rotatable about an axis that generally extends in the same direction as the handle housing in an elongated direction. The locking member has a first rotatable position wherein the switch is locked in its “off” position, and a second rotatable position wherein the switch is actuated to its “on” position. An actuating member allows a tool operator to move the locking member between its first and second positions.

15. 外观设计

USD467070S1 Screwdriver storage pouch 失效
标题翻译：螺丝刀储物袋
公开(公告)号：USD467070S1
公开(公告)日：2002-12-17
申请号：US29126084
申请日：2000-07-07
申请人： Gregory S. Snider , Matthew J. Holland
设计人： Gregory S. Snider , Matthew J. Holland

16. 外观设计

USD449443S1 Article carrier 失效
公开(公告)号：USD449443S1
公开(公告)日：2001-10-23
申请号：US29117823
申请日：2000-01-31
申请人： Gregory S. Snider
设计人： Gregory S. Snider

17. 发明授权

US06288350B1 Lockout mechanism for power tool 有权
标题翻译：电动工具闭锁机构
公开(公告)号：US06288350B1
公开(公告)日：2001-09-11
申请号：US09617306
申请日：2000-07-17
申请人： David C. Campbell , Lynn E. Lentino , Gregory S. Snider , Harry R. Hall
发明人： David C. Campbell , Lynn E. Lentino , Gregory S. Snider , Harry R. Hall
IPC分类号： H01H920
CPC分类号： H01H13/08 , H01H3/20 , H01H9/06
摘要： A switch lockout mechanism for a power tool includes a handle housing for gripping by a power tool operator. The handle housing is generally elongated in a direction corresponding to the gripping axis of a power tool operator. A switch is attached to the housing and is actuatable between an “on” position and an “off” position. A locking member is rotatably or pivotally attached to the housing. The locking member is rotatable about an axis that generally extends in the same direction as the handle housing in an elongated direction. The locking member has a first rotatable position wherein the switch is locked in its “off” position, and a second rotatable position wherein the switch is actuated to its “on” position. An actuating member allows a tool operator to move the locking member between its first and second positions.
摘要翻译：用于电动工具的开关锁定机构包括用于由电动工具操作者夹持的手柄壳体。手柄壳体通常在与电动工具操作者的夹持轴线相对应的方向上伸长。开关附接到壳体并且可以在“开”位置和“关”位置之间起动。锁定构件可旋转地或可枢转地附接到壳体。锁定构件可绕轴线旋转，所述轴线通常沿与手柄外壳沿长度方向相同的方向延伸。锁定构件具有第一可旋转位置，其中开关锁定在其“关闭”位置，以及第二可旋转位置，其中开关被致动到其“接通”位置。致动构件允许工具操作者在其第一和第二位置之间移动锁定构件。

18. 发明授权

US08605488B2 Capacitive crossbar arrays 有权
标题翻译：电容横杆阵列
公开(公告)号：US08605488B2
公开(公告)日：2013-12-10
申请号：US13256239
申请日：2009-06-12
申请人： Dmitri Borisovich Strukov , Gregory S. Snider , R. Stanley Williams
发明人： Dmitri Borisovich Strukov , Gregory S. Snider , R. Stanley Williams
IPC分类号： G11C11/24
CPC分类号： G11C13/00 , G11C11/24 , G11C23/00 , G11C2207/066
摘要： A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.
摘要翻译：电容式交叉开关阵列包括第一组导体和第二组导体，其相交以形成交叉点。非线性电容性装置插入在第一组内的第一导体和第二组中的交叉点处的第二导体之间。非线性电容性装置被配置为存储可通过所述第一导体和所述第二导体访问的信息。还提供了一种用于使用电容式交叉开关阵列的方法。

19. 发明申请

US20120014170A1 Capacitive Crossbar Arrays 有权
标题翻译：电容交叉开关阵列
公开(公告)号：US20120014170A1
公开(公告)日：2012-01-19
申请号：US13256239
申请日：2009-06-12
申请人： Dmitri Borisovich Strukov , Gregory S. Snider , R. Stanley Williams
发明人： Dmitri Borisovich Strukov , Gregory S. Snider , R. Stanley Williams
IPC分类号： G11C11/24
CPC分类号： G11C13/00 , G11C11/24 , G11C23/00 , G11C2207/066
摘要： A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is interposed between a first conductor (103) within the first set (102) and a second conductor (105) within the second set (104) at a crosspoint. The nonlinear capacitive device (106) is configured to store information which is accessible through said first conductor (103) and said second conductor (105). A method for utilizing a capacitive crossbar array (100) is also provided.
摘要翻译：电容纵横阵列（100）包括第一组导体（102）和第二组导体（104），其相交以形成交叉点。在第一组（102）内的第一导体（103）与第二组（104）内的第二导体（105）之间的交叉点处插入非线性电容性装置（106）。非线性电容性装置（106）被配置为存储可通过所述第一导体（103）和所述第二导体（105）访问的信息。还提供了一种用于使用电容式交叉开关阵列（100）的方法。

20. 发明申请

US20100277232A1 HYBRID MICROSCALE-NANOSCALE NEUROMORPHIC INTEGRATED CIRCUIT 有权
标题翻译：混合微结构纳米粒子神经网络集成电路
公开(公告)号：US20100277232A1
公开(公告)日：2010-11-04
申请号：US12743781
申请日：2008-05-22
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： H01L25/00
CPC分类号： G06N3/063 , G06N3/0635
摘要： Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer.
摘要翻译：本发明的实施例包括包含在集成电路基板上制造的模拟计算单元阵列的混合微纳米级纳米级神经元集成电路。每个计算单元内的模拟电子电路连接到第一类型的一个或多个引脚，并且连接到从计算单元大致垂直延伸的第二类型的一个或多个引脚。计算单元另外通过一个或多个纳米线互连层互连，每个纳米线互连层包括在忆阻子层的任一侧上的两个纳米线子层，互连层的每个纳米线子层中的每个纳米线连接到单个计算单元引脚和互连层的另一个纳米线子层中的多个纳米线。

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