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11. 发明申请

US20170178698A1 Memory Cell 有权
公开(公告)号：US20170178698A1
公开(公告)日：2017-06-22
申请号：US15369204
申请日：2016-12-05
申请人： IMEC VZW
发明人： Jan Van Houdt
IPC分类号： G11C7/06
CPC分类号： G11C7/06 , G11C16/0441 , G11C16/045 , G11C16/28 , H01L28/00 , H01L29/516 , H01L29/78 , H01L29/78391 , H01L29/788 , H01L29/792
摘要： The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.

12. 发明授权

US11296117B2 Three-dimensional ferroelectric memory 有权
公开(公告)号：US11296117B2
公开(公告)日：2022-04-05
申请号：US17112475
申请日：2020-12-04
申请人： IMEC vzw
发明人： Jan Van Houdt
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11585 , H01L27/11578 , H01L27/1158
摘要： The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

13. 发明授权

US11211404B2 Memory devices based on ferroelectric field effect transistors 有权
公开(公告)号：US11211404B2
公开(公告)日：2021-12-28
申请号：US16565112
申请日：2019-09-09
申请人： IMEC vzw
发明人： Shairfe Muhammad Salahuddin , Jan Van Houdt , Julien Ryckaert , Alessio Spessot
IPC分类号： G11C11/22 , H01L27/1159 , G11C11/4096 , H01L27/108 , H01L27/11587 , H01L27/11592
摘要： The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

14. 发明授权

US11211108B2 Ferroelectric memory device 有权
公开(公告)号：US11211108B2
公开(公告)日：2021-12-28
申请号：US16226356
申请日：2018-12-19
申请人： IMEC vzw
发明人： Jan Van Houdt
IPC分类号： G11C11/22 , H01L23/528 , H01L27/11507
摘要： The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.

15. 发明申请

US20210175254A1 THREE-DIMENSIONAL FERROELECTRIC MEMORY 有权
公开(公告)号：US20210175254A1
公开(公告)日：2021-06-10
申请号：US17112475
申请日：2020-12-04
申请人： IMEC vzw
发明人： Jan Van Houdt
IPC分类号： H01L27/11597 , H01L27/1159
摘要： The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

16. 发明授权

US10672894B2 Method of fabricating ferroelectric field-effect transistor 审中-公开
公开(公告)号：US10672894B2
公开(公告)日：2020-06-02
申请号：US16216833
申请日：2018-12-11
申请人： IMEC vzw
发明人： Jan Van Houdt , Hanns Christoph Adelmann , Han Chung Lin
IPC分类号： H01L29/66 , H01L29/51 , H01L29/16 , H01L29/78 , H01L21/02
摘要： The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

17. 发明申请

US20190198638A1 METHOD OF FABRICATING FERROELECTRIC FIELD-EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20190198638A1
公开(公告)日：2019-06-27
申请号：US16216833
申请日：2018-12-11
申请人： IMEC vzw
发明人： Jan Van Houdt , Hanns Christoph Adelmann , Han Chung Lin
IPC分类号： H01L29/66 , H01L21/02
摘要： The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

18. 发明申请

US20180102365A1 MEMORY DEVICE FOR A DYNAMIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：US20180102365A1
公开(公告)日：2018-04-12
申请号：US15729532
申请日：2017-10-10
申请人： IMEC vzw
发明人： Jan Van Houdt , Julien Ryckaert , Hyungrock Oh
IPC分类号： H01L27/108 , H01L21/8254 , G11C11/405
CPC分类号： H01L27/108 , G11C5/025 , G11C5/04 , G11C5/06 , G11C11/405 , G11C11/4076 , G11C11/4094 , G11C11/4097 , G11C13/004 , G11C13/0069 , G11C2213/71 , H01L21/8254 , H01L23/528 , H01L25/0657 , H01L27/10805 , H01L28/60
摘要： The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

19. 发明申请

US20170178712A1 PINCH-OFF FERROELECTRIC MEMORY 审中-公开
公开(公告)号：US20170178712A1
公开(公告)日：2017-06-22
申请号：US15385593
申请日：2016-12-20
申请人： IMEC VZW
发明人： Jan Van Houdt
IPC分类号： G11C11/22 , H01L27/1159
CPC分类号： G11C11/223 , G11C11/2273 , G11C16/0475 , H01L27/1159 , H01L29/6684 , H01L29/78391
摘要： The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.

20. 发明申请

US20220254795A1 FERROELECTRIC DEVICE BASED ON HAFNIUM ZIRCONATE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20220254795A1
公开(公告)日：2022-08-11
申请号：US17650154
申请日：2022-02-07
申请人： IMEC vzw
发明人： Mihaela Ioana Popovici , Amey Mahadev Walke , Jan Van Houdt
IPC分类号： H01L27/11507 , H01L49/02 , H01L29/78
摘要： A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.

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