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1. 发明授权

US11295977B2 Standard cell device and method of forming an interconnect structure for a standard cell device 有权
公开(公告)号：US11295977B2
公开(公告)日：2022-04-05
申请号：US16844442
申请日：2020-04-09
申请人： IMEC vzw
发明人： Juergen Boemmels , Julien Ryckaert
IPC分类号： H01L21/768 , G06F30/392 , H01L23/522
摘要： A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.

2. 发明授权

US10833161B2 Semiconductor device and method 有权
公开(公告)号：US10833161B2
公开(公告)日：2020-11-10
申请号：US16253321
申请日：2019-01-22
申请人： IMEC VZW , GLOBALFOUNDRIES INC.
发明人： Syed Muhammad Yasser Sherazi , Julien Ryckaert , Juergen Boemmels , Guillaume Bouche
IPC分类号： H01L29/417 , H01L29/78 , H01L21/311 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L23/522 , H01L29/08 , H01L29/66
摘要： A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

3. 发明申请

US20200328109A1 STANDARD CELL DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A STANDARD CELL DEVICE 审中-公开
公开(公告)号：US20200328109A1
公开(公告)日：2020-10-15
申请号：US16844442
申请日：2020-04-09
申请人： IMEC vzw
发明人： Juergen Boemmels , Julien Ryckaert
IPC分类号： H01L21/768 , H01L23/522 , G06F30/392
摘要： A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.

4. 发明申请

US20200312725A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200312725A1
公开(公告)日：2020-10-01
申请号：US16836478
申请日：2020-03-31
申请人： IMEC vzw
发明人： Anabela Veloso , Trong Huynh Bao , Julien Ryckaert , Raf Appeltans
IPC分类号： H01L21/8234
摘要： The disclosed technology relates to methods of fabricating field-effect transistors having channels extending in horizontal and vertical directions. According to an aspect, a method comprises: providing a semiconductor substrate comprising: in a vertical channel field-effect transistor (FET) device region, a first layer structure comprising a lower semiconductor layer, an intermediate semiconductor layer above the lower semiconductor layer and an upper semiconductor layer above the intermediate semiconductor layer, and, in a horizontal channel FET device region, a second layer structure comprising at least one semiconductor layer, wherein the first layer structure and the second layer structure have different compositions and wherein a surface of the substrate in the vertical channel FET device region is coplanar with a surface of the substrate in the horizontal channel FET device region; forming a mask defining a first semiconductor structure mask portion above the vertical channel FET device region and a second semiconductor structure mask portion above the horizontal channel FET device region; and patterning the first layer structure and the second layer structure by simultaneously etching the first layer structure and the second layer structure while using the mask as an etch mask, thereby forming: a first semiconductor structure for a vertical channel FET device in the vertical channel FET device region, the first semiconductor structure comprising a lower layer portion, an intermediate layer portion and an upper layer portion, and a second semiconductor structure for a horizontal channel FET device in the horizontal channel FET device region.

5. 发明申请

US20200135568A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
公开(公告)号：US20200135568A1
公开(公告)日：2020-04-30
申请号：US16663796
申请日：2019-10-25
申请人： IMEC vzw
发明人： Juergen Boemmels , Julien Ryckaert
IPC分类号： H01L21/8234 , H01L29/423
摘要： The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.

6. 发明申请

US20180113975A1 METHOD OF PATTERNING TARGET LAYER 审中-公开
公开(公告)号：US20180113975A1
公开(公告)日：2018-04-26
申请号：US15791210
申请日：2017-10-23
申请人： IMEC VZW , GLOBALFOUNDRIES INC.
发明人： Syed Muhammad Yasser Sherazi , Guillaume Bouche , Julien Ryckaert
IPC分类号： G06F17/50 , H01L21/033 , H01L21/308 , H01L21/762 , H01L21/84 , H01L27/02 , H01L27/11 , H01L27/12
摘要： The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

7. 发明申请

US20170062421A1 BURIED INTERCONNECT FOR SEMICONDUCTOR CIRCUITS 审中-公开
标题翻译：用于半导体电路的双绞互连
公开(公告)号：US20170062421A1
公开(公告)日：2017-03-02
申请号：US15247127
申请日：2016-08-25
申请人： IMEC VZW
发明人： Stefan Cosemans , Praveen Raghavan , Steven Demuynck , Julien Ryckaert
IPC分类号： H01L27/088 , H01L21/768 , H01L21/8234 , H01L23/528 , H01L27/02
CPC分类号： H01L27/0886 , H01L21/743 , H01L21/76895 , H01L21/823431 , H01L21/823475 , H01L23/485 , H01L23/5286 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L28/00 , H01L29/785
摘要： A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.
摘要翻译：半导体电路包括包括多个晶体管的线路前端（FEOL），每个晶体管具有源极区域，漏极区域和布置在源极区域和漏极区域之间并包括栅电极的栅极区域。半导体电路还包括布置在FEOL中的埋入式互连件，并且从栅极区域从栅极电极的底部接触部分电连接到栅极区域。通过使用埋地互连，可以方便地进行电路的布线。

8. 发明公开

US20230386928A1 Method for Forming a Stacked Transistor Device 审中-公开
公开(公告)号：US20230386928A1
公开(公告)日：2023-11-30
申请号：US18322213
申请日：2023-05-23
申请人： IMEC VZW
发明人： Boon Teik Chan , Naoto Horiguchi , Julien Ryckaert
IPC分类号： H01L21/8234 , H01L29/66
CPC分类号： H01L21/823456 , H01L21/823412 , H01L21/823431 , H01L29/66439
摘要： The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.

9. 发明公开

US20230197522A1 Method for Forming a Semiconductor Device 审中-公开
公开(公告)号：US20230197522A1
公开(公告)日：2023-06-22
申请号：US18065130
申请日：2022-12-13
申请人： IMEC VZW
发明人： Boon Teik Chan , Anne Vandooren , Julien Ryckaert , Naoto Horiguchi
IPC分类号： H01L21/8234 , H01L29/66
CPC分类号： H01L21/823437 , H01L29/66545 , H01L29/66553 , H01L29/42392
摘要： The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack. The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

10. 发明公开

US20230197514A1 Metallization Process for an Integrated Circuit 审中-公开
公开(公告)号：US20230197514A1
公开(公告)日：2023-06-22
申请号：US18066400
申请日：2022-12-15
申请人： IMEC VZW
发明人： Victor Hugo Vega Gonzalez , Bilal Chehab , Julien Ryckaert , Zsolt Tokei , Serge Biesemans , Naoto Horiguchi
IPC分类号： H01L21/768 , H01L21/3213 , H01L23/522
CPC分类号： H01L21/76897 , H01L21/32139 , H01L21/76885 , H01L23/5226 , H01L21/32136 , H01L27/092
摘要： The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

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