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11. 发明申请

US20160371036A1 TRANSACTIONAL MEMORY MANAGEMENT TECHNIQUES 审中-公开
公开(公告)号：US20160371036A1
公开(公告)日：2016-12-22
申请号：US15160786
申请日：2016-05-20
申请人： Intel Corporation
发明人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman
IPC分类号： G06F3/06 , G06F9/46
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/067 , G06F3/0673 , G06F9/44 , G06F9/466 , G06F9/467 , G06F12/0813
摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

12. 发明授权

US09507714B2 Managed runtime extensions to reduce power consumption in devices with hybrid memory 有权
标题翻译：受管理的运行时扩展，以减少具有混合内存的设备的功耗
公开(公告)号：US09507714B2
公开(公告)日：2016-11-29
申请号：US14227432
申请日：2014-03-27
申请人： Intel Corporation
发明人： Stephan A. Herhut , Richard L. Hudson , Tatiana Shpeisman
IPC分类号： G06F12/02
CPC分类号： G06F12/0276 , G06F12/0238 , G06F2212/1028 , G06F2212/1041 , G06F2212/205 , G06F2212/7202 , G06F2212/7205 , Y02D10/13
摘要： Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.
摘要翻译：系统和方法可以提供用于识别被管理的运行时环境中的对象并且在所管理的运行时环境的软件级别确定对象的年龄。另外，可以至少部分地基于对象的年龄，将对象选择性地分配在动态随机存取存储器（DRAM）或非易失性随机存取存储器（NVRAM）之一中。在一个示例中，还确定对象的数据类型，其中基于数据类型有选择地分配对象。

13. 发明授权

US09361152B2 Transactional memory management techniques 有权
标题翻译：事务性内存管理技术
公开(公告)号：US09361152B2
公开(公告)日：2016-06-07
申请号：US14129936
申请日：2013-07-15
申请人： Intel Corporation
发明人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman
IPC分类号： G06F12/10 , G06F9/46 , G06F9/44 , G06F12/08 , G06F3/06
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/067 , G06F3/0673 , G06F9/44 , G06F9/466 , G06F9/467 , G06F12/0813
摘要： Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.
摘要翻译：描述了改进的事务性内存管理技术。在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件当执行硬件事务完成时，全局锁活动时的事务。描述和要求保护其他实施例。

14. 发明申请

US20150186273A1 METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM 审中-公开
标题翻译：在异位平台上配置共享点的方法和装置
公开(公告)号：US20150186273A1
公开(公告)日：2015-07-02
申请号：US14513065
申请日：2014-10-13
申请人： Intel Corporation
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译：一种促进异构平台中的共享指针的方法和装置。在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的处理核心。异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。

15. 发明申请

US20220391679A1 SPECIALIZED FIXED FUNCTION HARDWARE FOR EFFICIENT CONVOLUTION 有权
公开(公告)号：US20220391679A1
公开(公告)日：2022-12-08
申请号：US17886055
申请日：2022-08-11
申请人： Intel Corporation
发明人： Rajkishore Barik , Elmoustapha Ould-Ahmed-Vall , Xiaoming Chen , Dhawal Srivastava , Anbang Yao , Kevin Nealis , Eriko Nurvitadhi , Sara S. Baghsorkhi , Balaji Vembu , Tatiana Shpeisman , Ping T. Tang
IPC分类号： G06N3/063 , G06N3/04 , G06F9/30 , G06F9/38 , G06T1/20 , G06N3/08 , G06F16/17
摘要： One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

16. 发明授权

US11360933B2 Graphics processing integrated circuit package 有权
公开(公告)号：US11360933B2
公开(公告)日：2022-06-14
申请号：US16744407
申请日：2020-01-16
申请人： Intel Corporation
发明人： Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
IPC分类号： G06F15/80 , G06F13/40 , G06T1/20 , G06F9/30 , G06F13/00 , G06N3/04 , G06N3/063 , G06N3/08
摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

17. 发明授权

US11138048B2 Work stealing in heterogeneous computing systems 有权
公开(公告)号：US11138048B2
公开(公告)日：2021-10-05
申请号：US15391549
申请日：2016-12-27
申请人： Intel Corporation
发明人： Rajkishore Barik , Stephan A. Herhut , Jaswanth Sreeram , Tatiana Shpeisman , Richard L. Hudson
IPC分类号： G06F9/50 , G06F13/42
摘要： A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.

18. 发明申请

US20210264163A1 PERSON TRACKING AND PRIVACY AND ACCELERATION OF DATA USING AUTONOMOUS MACHINES 有权
公开(公告)号：US20210264163A1
公开(公告)日：2021-08-26
申请号：US17173732
申请日：2021-02-11
申请人： Intel Corporation
发明人： Mayuresh M. Varerkar , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Sherine Abdelhak , Sachin Godse , Farshad Akhbari , Narayan Srinivasa , Altug Koker , Nadathur Rajagopalan Satish , Dukhwan Kim , Feng Chen , Abhishek R. Appu , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06K9/00 , G06T1/20 , G06N3/04 , G06N3/08 , G06N3/063
摘要： A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

19. 发明授权

US11080046B2 Instructions and logic to perform floating point and integer operations for machine learning 有权
公开(公告)号：US11080046B2
公开(公告)日：2021-08-03
申请号：US17169232
申请日：2021-02-05
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06F9/302 , G06F7/483 , G06N3/04 , G06F17/16 , G06F9/30 , G09G5/393 , G06F7/544 , G06F9/38 , G06N3/08 , G06N3/063 , G06N20/00 , G06T15/00
摘要： A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

20. 发明授权

US10922553B2 Person tracking and privacy and acceleration of data using autonomous machines 有权
公开(公告)号：US10922553B2
公开(公告)日：2021-02-16
申请号：US16379176
申请日：2019-04-09
申请人： Intel Corporation
发明人： Mayuresh M. Varerkar , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Sherine Abdelhak , Sachin Godse , Farshad Akhbari , Narayan Srinivasa , Altug Koker , Nadathur Rajagopalan Satish , Dukhwan Kim , Feng Chen , Abhishek R. Appu , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： H04N5/225 , H04N3/20 , H04N5/228 , G06K9/00 , G06T1/20 , G06N3/04 , G06N3/08 , G06N3/063 , H04N7/14 , H04N5/38
摘要： A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

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