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1. 发明申请

US20230046506A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：US20230046506A1
公开(公告)日：2023-02-16
申请号：US17967283
申请日：2022-10-17
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06F9/30 , G06F7/483 , G06N3/063 , G06N3/04 , G06F9/38 , G06N3/08 , G09G5/393 , G06F7/544 , G06T15/00 , G06N20/00 , G06F17/16
摘要： One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

2. 发明授权

US11475286B2 Specialized fixed function hardware for efficient convolution 有权
公开(公告)号：US11475286B2
公开(公告)日：2022-10-18
申请号：US17558285
申请日：2021-12-21
申请人： Intel Corporation
发明人： Rajkishore Barik , Elmoustapha Ould-Ahmed-Vall , Xiaoming Chen , Dhawal Srivastava , Anbang Yao , Kevin Nealis , Eriko Nurvitadhi , Sara S. Baghsorkhi , Balaji Vembu , Tatiana Shpeisman , Ping T. Tang
IPC分类号： G06N3/06 , G06N3/063 , G06N3/04 , G06F9/30 , G06F9/38 , G06T1/20 , G06N3/08 , G06F16/17
摘要： One embodiment provides an apparatus comprising an instruction cache to store a plurality of instructions, a scheduler unit coupled to the instruction cache, the scheduler unit to schedule the plurality of instructions for execution, an instruction fetch and decode unit to decode the plurality of instructions to determine a set of operations to perform in response, one or more compute blocks to perform parallel multiply-accumulate operations based on the instruction fetch and decode unit decoding a first instruction of the plurality of instructions, and matrix multiplication logic to perform matrix multiplication operations based on the instruction fetch and decode unit decoding a second instruction of the plurality of instructions.

3. 发明申请

US20220027210A1 Work Stealing in Heterogeneous Computing Systems 有权
公开(公告)号：US20220027210A1
公开(公告)日：2022-01-27
申请号：US17493419
申请日：2021-10-04
申请人： Intel Corporation
发明人： Rajkishore Barik , Stephan A. Herhut , Jaswanth Sreeram , Tatiana Shpeisman , Richard L. Hudson
IPC分类号： G06F9/50 , G06F13/42
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate a second task from the workload to a second work queue, second computation circuitry to process the second task in the second work queue. The apparatus further includes first work stealer logic to steal the second task from the second work queue using an atomic operation to access the second work queue.

4. 发明授权

US11169799B2 Instructions and logic to perform floating-point and integer operations for machine learning 有权
公开(公告)号：US11169799B2
公开(公告)日：2021-11-09
申请号：US16432402
申请日：2019-06-05
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06F9/30 , G06F9/38 , G06F7/483 , G06F7/544 , G06N3/063 , G06N20/00 , G09G5/393 , G06N3/04 , G06N3/08 , G06T15/00
摘要： One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

5. 发明申请

US20210182058A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：US20210182058A1
公开(公告)日：2021-06-17
申请号：US17169232
申请日：2021-02-05
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark A. Anders , Sanu K. Mathew , Anbang Yao , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Rajkishore Barik , Tsung-Han Lin , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06F9/30 , G06N3/04 , G06F9/38 , G06F7/483 , G09G5/393 , G06F7/544 , G06N3/063 , G06N3/08
摘要： A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

6. 发明授权

US10824938B2 Specialized fixed function hardware for efficient convolution 有权
公开(公告)号：US10824938B2
公开(公告)日：2020-11-03
申请号：US15494723
申请日：2017-04-24
申请人： Intel Corporation
发明人： Rajkishore Barik , Elmoustapha Ould-Ahmed-Vall , Xiaoming Chen , Dhawal Srivastava , Anbang Yao , Kevin Nealis , Eriko Nurvitadhi , Sara S. Baghsorkhi , Balaji Vembu , Tatiana Shpeisman , Ping T. Tang
IPC分类号： G06N3/06 , G06N3/063 , G06N3/04 , G06F9/30 , G06F9/38 , G06T1/20 , G06N3/08
摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to perform one or more machine learning operations, wherein the decode unit, based on parameters of the one or more machine learning operations, is to request a scheduler to schedule the one or more machine learning operations to one of an array of programmable compute units and a fixed function compute unit.

7. 发明授权

US10409614B2 Instructions having support for floating point and integer data types in the same register 有权
公开(公告)号：US10409614B2
公开(公告)日：2019-09-10
申请号：US15494773
申请日：2017-04-24
申请人： Intel Corporation
发明人： Elmoustapha Ould-Ahmed-Vall , Barath Lakshmanan , Tatiana Shpeisman , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Anbang Yao , Ben J. Ashbaugh , Linda L. Hurd , Liwei Ma
IPC分类号： G06F9/38 , G06N3/00 , G06F15/80 , G06F9/50 , G06N3/08 , G06N3/063 , G06N3/04 , G06N20/00 , G06F9/30 , G06T1/20 , G06F13/42 , G06F13/40
摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.

8. 发明申请

US20180299841A1 AUTONOMOUS VEHICLE NEURAL NETWORK OPTIMIZATION 审中-公开
公开(公告)号：US20180299841A1
公开(公告)日：2018-10-18
申请号：US15489142
申请日：2017-04-17
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. MacPherson , John C. Weast , Justin E. Gottschlich , Jingyi Jin , Barath Lakshmanan , Chandrasekaran Sakthivel , Michael S. Strickland , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Balaji Vembu , Ping T. Tang , Anbang Yao , Tatiana Shpeisman , Xiaoming Chen , Vasanth Ranganathan , Sanjeev S. Jahagirdar
IPC分类号： G05B13/02 , G05D1/00 , G06N3/04 , G06N3/02 , G06N5/04 , G06N99/00
摘要： Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.

9. 发明授权

US09690552B2 Technologies for low-level composable high performance computing libraries 有权
公开(公告)号：US09690552B2
公开(公告)日：2017-06-27
申请号：US14583657
申请日：2014-12-27
申请人： Intel Corporation
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Paul M. Petersen , Victor W. Lee , P. G. Lowney , Arch D. Robison , Cheng Wang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

10. 发明授权

US09588801B2 Apparatus and method for improved lock elision techniques 有权
标题翻译：用于改进锁定检测技术的装置和方法
公开(公告)号：US09588801B2
公开(公告)日：2017-03-07
申请号：US14024451
申请日：2013-09-11
申请人： Intel Corporation
发明人： Irina Calciu , Justin E Gottschlich , Tatiana Shpeisman , Gilles A Pokam
IPC分类号： G06F9/30 , G06F9/46 , G06F12/14 , G06F9/52
CPC分类号： G06F9/467 , G06F9/30181 , G06F9/526 , G06F12/1466
摘要： An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.
摘要翻译：一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。

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