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11. 发明申请

US20140254297A1 METHOD AND APPARATUS FOR MEMORY REPAIR 有权
标题翻译：用于记忆修复的方法和装置
公开(公告)号：US20140254297A1
公开(公告)日：2014-09-11
申请号：US14036997
申请日：2013-09-25
申请人： Macronix International Co., Ltd.
发明人： Shuo-Nan Hung , Chi Lo , Chun-Hsiung Hung
IPC分类号： G11C29/04
CPC分类号： G11C29/70 , G11C29/04 , G11C29/72 , G11C29/808 , G11C29/82
摘要： An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
摘要翻译：集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。主列和冗余列分为行块。位线将主列连接到指示冗余列修复状态的状态存储器。集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器进行更新。或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

12. 发明申请

US20140098616A1 METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY 有权
标题翻译：用于减少存储器中读取干扰的方法和装置
公开(公告)号：US20140098616A1
公开(公告)日：2014-04-10
申请号：US14105920
申请日：2013-12-13
申请人： Macronix International Co., Ltd.
发明人： Chun Hsiung Hung , Shuo-Nan Hung , Tseng-Yi Liu
IPC分类号： G11C16/34
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
摘要翻译： NAND存储器的各个方面包括控制电路，该控制电路通过测量在串联的第一端和第二端之间流动的电流来将读偏置装置施加到多个字线以读取存储在多个存储单元上的选定数据值的记忆细胞。读取偏置布置被施加到多个字线的字线仅施加小于第二阈值电压分布的第二最大值的字线电压。

13. 发明申请

US20140056072A1 3D MEMORY ARRAY WITH READ BIT LINE SHIELDING 有权
标题翻译：具有读取位线屏蔽的3D存储阵列
公开(公告)号：US20140056072A1
公开(公告)日：2014-02-27
申请号：US14066450
申请日：2013-10-29
申请人： Macronix International Co., Ltd.
发明人： Shuo-Nan Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , H01L23/5225 , H01L27/11578 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.
摘要翻译：存储器件包括具有多个电平的存储器单元块。每个级别包括在块的第一和第二端之间沿第一方向延伸的存储器单元条。在第一端的每个级别处的第一位线结构耦合到从第一端延伸的第一串存储器单元。在第二端的每个级别处的第二位线结构耦合到从所述第二端延伸的第二存储单元串。位线对在第一个方向上延伸，每个包括奇数和偶数位线。奇偶位线连接器将奇数位和偶数位线分别连接到第二和第一位线结构。一系列位线对的每个位线由相邻位线对的位线分开。

14. 发明授权

US11630786B2 Non-sequential page continuous read 有权
公开(公告)号：US11630786B2
公开(公告)日：2023-04-18
申请号：US17321193
申请日：2021-05-14
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shuo-Nan Hung
IPC分类号： G06F13/16 , G06F3/06 , G06F11/10 , G11C29/52
摘要： A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

15. 发明申请

US20230015202A1 DATA RETENTION IN MEMORY DEVICES 有权
公开(公告)号：US20230015202A1
公开(公告)日：2023-01-19
申请号：US17953439
申请日：2022-09-27
申请人： Macronix International Co., Ltd.
发明人： Shuo-Nan Hung , E-Yuan Chang
IPC分类号： G06F3/06
摘要： A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

16. 发明授权

US11455254B2 Flash memory system and flash memory device thereof 有权
公开(公告)号：US11455254B2
公开(公告)日：2022-09-27
申请号：US17118239
申请日：2020-12-10
申请人： MACRONIX International Co., Ltd.
发明人： Chun-Lien Su , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G06F12/0882 , G06F11/10 , G06F12/02 , G06F12/0862
摘要： A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

17. 发明授权

US11182302B2 Memory device, electronic device, and associated read method 有权
公开(公告)号：US11182302B2
公开(公告)日：2021-11-23
申请号：US16820795
申请日：2020-03-17
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chun-Lien Su , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G06F12/08 , G06F12/0882 , G06F12/0862 , G11C7/22 , G06F9/30 , G06F12/0893
摘要： A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

18. 发明授权

US09773571B2 Memory repair redundancy with array cache redundancy 有权
公开(公告)号：US09773571B2
公开(公告)日：2017-09-26
申请号：US14572166
申请日：2014-12-16
申请人： Macronix International Co., Ltd.
发明人： Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/78 , G06F2201/85 , G11C29/76
摘要： An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.

19. 发明申请

US20160170853A1 MEMORY REPAIR REDUNDANCY 有权
标题翻译：记忆修复冗余
公开(公告)号：US20160170853A1
公开(公告)日：2016-06-16
申请号：US14572166
申请日：2014-12-16
申请人： Macronix International Co., Ltd.
发明人： Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G06F11/20 , G11C29/00
CPC分类号： G11C29/78 , G06F2201/85 , G11C29/76
摘要： An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.
摘要翻译：描述了包括存储器，阵列高速缓存和高速缓存替换存储器的集成电路。内存包括主阵列和冗余阵列。集成电路还包括被配置为使用数组高速缓存将数据传入或传出主阵列的电路。对于阵列高速缓存中的不良位置，电路被配置为在代替数据高速缓存中的有缺陷的位置的数据传输中使用高速缓存替换存储器，并且对应于高速缓存阵列中的缺陷位置的映射地址到冗余阵列。

20. 发明授权

US09165680B2 Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks 有权
标题翻译：具有能够仅存储主列块的行块的子集的页寄存器/状态存储器的存储器集成电路
公开(公告)号：US09165680B2
公开(公告)日：2015-10-20
申请号：US14036997
申请日：2013-09-25
申请人： Macronix International Co., Ltd.
发明人： Shuo-Nan Hung , Chi Lo , Chun-Hsiung Hung
IPC分类号： G11C29/04 , G11C29/00
CPC分类号： G11C29/70 , G11C29/04 , G11C29/72 , G11C29/808 , G11C29/82
摘要： An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
摘要翻译：集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。主列和冗余列分为行块。位线将主列连接到指示冗余列修复状态的状态存储器。集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器执行更新。或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

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