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1. 发明授权

US11550494B2 Method to support high reliability multiple times program non-volatile configuration setting 有权
公开(公告)号：US11550494B2
公开(公告)日：2023-01-10
申请号：US17166804
申请日：2021-02-03
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shuo-Nan Hung
IPC分类号： G06F3/06
摘要： A method provides the capability to maintain a configuration settings data image stored by a non-volatile memory device. The configuration settings data image can be multiple times programmed (MTP) without sacrificing reliability of the semiconductor device in the event of spurious power fluctuations, intermittent or bad memory storage blocks storing the configuration settings data image.

2. 发明授权

US11249913B2 Continuous read with multiple read commands 有权
公开(公告)号：US11249913B2
公开(公告)日：2022-02-15
申请号：US17061451
申请日：2020-10-01
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shuo-Nan Hung , Chun-Lien Su
IPC分类号： G06F12/08 , G06F12/0882
摘要： A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

3. 发明授权

US09690650B2 Storage scheme for built-in ECC operations 有权
公开(公告)号：US09690650B2
公开(公告)日：2017-06-27
申请号：US13951130
申请日：2013-07-25
申请人： Macronix International Co., Ltd.
发明人： Yi-Ching Liu , Chi Lo , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C29/00 , G06F11/10 , G11B20/18 , G11C7/10
CPC分类号： G06F11/1044 , G06F11/1008 , G06F11/1068 , G11B20/1833 , G11C7/1006
摘要： A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

4. 发明申请

US20220188238A1 FLASH MEMORY SYSTEM AND FLASH MEMORY DEVICE THEREOF 有权
公开(公告)号：US20220188238A1
公开(公告)日：2022-06-16
申请号：US17118239
申请日：2020-12-10
申请人： MACRONIX International Co., Ltd.
发明人： Chun-Lien Su , Chun-Hsiung Hung , Shuo-Nan Hung
IPC分类号： G06F12/0882 , G06F12/0862 , G06F12/02 , G06F11/10
摘要： A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

5. 发明授权

US10977121B2 Fast page continuous read 有权
公开(公告)号：US10977121B2
公开(公告)日：2021-04-13
申请号：US16533463
申请日：2019-08-06
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G06F11/10 , H03M13/15 , G11C11/4093 , G11C11/4094
摘要： A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

6. 发明授权

US10957384B1 Page buffer structure and fast continuous read 有权
公开(公告)号：US10957384B1
公开(公告)日：2021-03-23
申请号：US16581562
申请日：2019-09-24
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Ji-Yu Hung , Shuo-Nan Hung
IPC分类号： G11C16/06 , G11C11/4094 , G11C29/00 , G11C29/42 , G11C11/4093
摘要： A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

7. 发明授权

US10325662B2 Circuit and method for adjusting select gate voltage of non-volatile memory during erasure of memory cells based on a well voltage 有权
公开(公告)号：US10325662B2
公开(公告)日：2019-06-18
申请号：US15705001
申请日：2017-09-14
申请人： MACRONIX International Co., Ltd.
发明人： Shuo-Nan Hung , Shin-Jang Shen , Wei-Jen Chen
IPC分类号： G11C11/34 , G11C16/06 , G11C16/14 , G11C16/04 , G11C16/08
摘要： A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

8. 发明授权

US09152557B2 Program method, data recovery method, and flash memory using the same 有权
标题翻译：程序方法，数据恢复方法和闪存使用相同
公开(公告)号：US09152557B2
公开(公告)日：2015-10-06
申请号：US14265400
申请日：2014-04-30
申请人： Macronix International Co., Ltd.
发明人： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
IPC分类号： G06F3/06 , G06F12/02 , G11C16/10 , G11C11/56 , G06F11/00
CPC分类号： G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
摘要： A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
摘要翻译：提供了一种用于多级单元（MLC）闪速存储器的程序方法。存储器阵列包括对应于各个页面的多个页面和多个配对页面。程序方法包括以下步骤。首先，获得程序地址命令。接下来，确定与配对页中的任何一个对应的程序地址命令。当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。之后，第一个配对的页面被编程。

9. 发明授权

US09136006B2 Method and device for reducing coupling noise during read operation 有权
标题翻译：在读取操作期间减少耦合噪声的方法和装置
公开(公告)号：US09136006B2
公开(公告)日：2015-09-15
申请号：US13946123
申请日：2013-07-19
申请人： Macronix International Co., Ltd.
发明人： Shuo-Nan Hung , Ji-Yu Hung
IPC分类号： G11C16/26 , G11C16/24 , G11C16/28
CPC分类号： G11C16/26 , G11C16/24 , G11C16/28
摘要： A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.
摘要翻译：提供了一种用于感测存储器件中的数据的方法。存储器件包括耦合到多个位线的存储器单元块。该方法包括将多个位线预充电到第一级VPRE。该方法包括实现电流流过多条位线上的选定存储单元到参考线或耦合到参考电压的参考线。该方法包括防止由于位线上的电流而导致的电压变化导致位线电压超出第一电平和第二电平VKEEP之间的范围，其中第二电平低于第一电平，高于参考电压。该方法包括感测所选存储单元中的数据。

10. 发明授权

US08976600B2 Word line driver circuit for selecting and deselecting word lines 有权
标题翻译：用于选择和取消选择字线的字线驱动电路
公开(公告)号：US08976600B2
公开(公告)日：2015-03-10
申请号：US14046428
申请日：2013-10-04
申请人： Macronix International Co., Ltd.
发明人： Chun-Hsiung Hung , Ti Wen Chen , Shuo-Nan Hung , Shih-Lin Huang
IPC分类号： G11C16/06 , G11C16/16
CPC分类号： G11C16/16 , G11C16/08 , G11C16/12
摘要： A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.
摘要翻译：存储电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

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