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11. 发明申请

US20170263641A1 Three-Dimensional Semiconductor Memory Devices 审中-公开
公开(公告)号：US20170263641A1
公开(公告)日：2017-09-14
申请号：US15602886
申请日：2017-05-23
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/11565 , H01L29/792 , H01L27/1157
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

12. 发明申请

US20160247817A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20160247817A1
公开(公告)日：2016-08-25
申请号：US15142533
申请日：2016-04-29
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

13. 发明授权

US09236340B2 String selection structure of three-dimensional semiconductor device 有权
标题翻译：三维半导体器件的串选择结构
公开(公告)号：US09236340B2
公开(公告)日：2016-01-12
申请号：US14088127
申请日：2013-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Sung-Min Hwang
IPC分类号： G11C16/10 , H01L23/50 , G11C16/08 , G11C11/56 , G11C16/04 , H01L27/115
CPC分类号： H01L23/50 , G11C11/5635 , G11C16/0483 , G11C16/08 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.
摘要翻译：三维半导体器件包括彼此堆叠的第一和第二选择线。水平地横越第一和第二选择线的上线。第一和第二垂直图案垂直地跨越第一和第二选择线。第一和第二垂直图案共同连接到上线。第一和第二垂直图案中的每一个构成彼此串联连接的第一和第二选择晶体管。第一和第二垂直图案的第一选择晶体管分别由第一和第二选择线控制。

14. 发明授权

US09000508B2 Nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：在其中具有垂直集成的非易失性存储单元子串的非易失性存储器件
公开(公告)号：US09000508B2
公开(公告)日：2015-04-07
申请号：US14024844
申请日：2013-09-12
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Sunhil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L29/66 , H01L29/78 , H01L29/792 , G11C16/28 , H01L27/115 , H01L29/788
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：根据本发明的实施例的非易失性存储器件包括高度集成的非易失性存储器单元的垂直堆叠。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

15. 发明申请

US20200258908A1 SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20200258908A1
公开(公告)日：2020-08-13
申请号：US16860113
申请日：2020-04-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L27/11582 , H01L29/792 , H01L29/06 , H01L27/11578 , H01L27/11556 , H01L27/11551
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

16. 发明授权

US10096616B2 Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate 有权
公开(公告)号：US10096616B2
公开(公告)日：2018-10-09
申请号：US15593494
申请日：2017-05-12
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Heonkyu Lee , Shinhwan Kang , Youngwoo Park
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11565 , H01L23/528
摘要： A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

17. 发明授权

US09905574B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US09905574B2
公开(公告)日：2018-02-27
申请号：US15602886
申请日：2017-05-23
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

18. 发明授权

US09754957B2 Nonvolatile memory devices and methods forming the same 有权
公开(公告)号：US09754957B2
公开(公告)日：2017-09-05
申请号：US14682111
申请日：2015-04-09
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son
IPC分类号： H01L27/11582 , G11C16/04 , H01L27/11556 , H01L21/28 , H01L23/50 , H01L27/11524 , H01L27/1157
CPC分类号： H01L27/11582 , G11C16/0408 , G11C16/0483 , H01L21/28008 , H01L23/50 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L2924/00 , H01L2924/0002
摘要： Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

19. 发明授权

US09595346B2 3-Dimensional semiconductor memory device and operating method thereof 有权
标题翻译： 3维半导体存储器件及其操作方法
公开(公告)号：US09595346B2
公开(公告)日：2017-03-14
申请号：US15157720
申请日：2016-05-18
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Dohyun Lee , Youngwoo Park , Su Jin Ahn , Jaeduk Lee
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10 , G11C16/04 , H01L27/115 , H01L23/528 , H01L29/04 , H01L29/16
CPC分类号： H01L27/11524 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/04 , H01L29/16
摘要： Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.
摘要翻译：公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号单元格阵列。电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案，第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。

20. 发明授权

US10748929B2 Three-dimensional semiconductor devices 有权
公开(公告)号：US10748929B2
公开(公告)日：2020-08-18
申请号：US16739417
申请日：2020-01-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/06 , H01L29/792
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

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