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1. 发明授权

US09356159B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US09356159B2
公开(公告)日：2016-05-31
申请号：US14830299
申请日：2015-08-19
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

2. 发明授权

US10685844B2 Hardmask composition, method of forming pattern by using the hardmask composition, and hardmask formed using the hardmask composition 有权
公开(公告)号：US10685844B2
公开(公告)日：2020-06-16
申请号：US16036113
申请日：2018-07-16
申请人： Samsung Electronics Co., Ltd. , Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
发明人： Sangwon Kim , Changsik Song , Dongcheol Jeong , Minsu Seol , Hyeonjin Shin , Dongwook Lee , Taewoo Kim , Juhyen Lee , Hyejin Cho
IPC分类号： H01L21/308 , H01L29/16 , C07B37/12 , G03F7/004 , H01L21/311 , G03F7/16 , G03F7/027 , H01L21/033 , G03F7/09 , C08L101/02 , B82Y30/00 , C07C15/20 , C07C39/14 , C07C63/337 , H01L29/66
摘要： Provided are a hardmask composition, a method of forming a pattern using the hardmask composition, and a hardmask formed using the hardmask composition. The hardmask composition includes a polar nonaqueous organic solvent and one of: i) a mixture of graphene quantum dots and at least one selected from a diene and a dienophile, ii) a Diels-Alder reaction product of the graphene quantum dots and the at least one selected from a diene and a dienophile, iii) a thermal treatment product of the Diels-Alder reaction product of graphene quantum dots and the at least one selected from a diene and a dienophile, or iv) a combination thereof.

3. 发明申请

US20180151590A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20180151590A1
公开(公告)日：2018-05-31
申请号：US15871375
申请日：2018-01-15
申请人： Samsung Electronics Co., Ltd.
发明人： CHANGHYUN LEE , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L29/792 , H01L27/1157 , H01L27/11565
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

4. 发明授权

US09905574B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US09905574B2
公开(公告)日：2018-02-27
申请号：US15602886
申请日：2017-05-23
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

5. 发明申请

US20150357345A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：三维半导体存储器件
公开(公告)号：US20150357345A1
公开(公告)日：2015-12-10
申请号：US14830299
申请日：2015-08-19
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
摘要翻译：三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。凹部部分（或完全）延伸穿过公共源区域。衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直叠层的侧壁上并在凹槽的侧壁上延伸。栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

6. 发明授权

US09136395B2 Three-dimensional semiconductor memory devices 有权
标题翻译：三维半导体存储器件
公开(公告)号：US09136395B2
公开(公告)日：2015-09-15
申请号：US14057380
申请日：2013-10-18
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
摘要翻译：三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。凹部部分（或完全）延伸穿过公共源区域。衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直叠层的侧壁上并在凹槽的侧壁上延伸。栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

7. 发明授权

US10978479B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US10978479B2
公开(公告)日：2021-04-13
申请号：US16804982
申请日：2020-02-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/792
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

8. 发明授权

US10600801B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US10600801B2
公开(公告)日：2020-03-24
申请号：US15871375
申请日：2018-01-15
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/792
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

9. 发明授权

US09793292B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US09793292B2
公开(公告)日：2017-10-17
申请号：US15142533
申请日：2016-04-29
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

10. 发明申请

US20170263641A1 Three-Dimensional Semiconductor Memory Devices 审中-公开
公开(公告)号：US20170263641A1
公开(公告)日：2017-09-14
申请号：US15602886
申请日：2017-05-23
申请人： Samsung Electronics Co., Ltd.
发明人： Changhyun Lee , Byoungkeun Son , Hyejin Cho
IPC分类号： H01L27/11582 , H01L27/11565 , H01L29/792 , H01L27/1157
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

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