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11. 发明授权

US08415756B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08415756B2
公开(公告)日：2013-04-09
申请号：US12870486
申请日：2010-08-27
申请人： Keisuke Tsukamoto , Shinya Hirano , Yuichiro Fujiyama , Tatsunori Murata
发明人： Keisuke Tsukamoto , Shinya Hirano , Yuichiro Fujiyama , Tatsunori Murata
IPC分类号： H01L29/82
CPC分类号： H01L27/105 , H01L27/228 , H01L43/08 , H01L43/12
摘要： There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.
摘要翻译：提供一种半导体器件，其中减小了电阻元件等中的短路故障及其制造方法。其中形成存储单元的层间绝缘膜形成为使得位于形成有磁阻元件的存储单元区域中的层间绝缘膜的部分的上表面位于比上表面的位置低的位置层间绝缘膜的位于周边区域的部分。形成另一层间绝缘膜以覆盖磁阻元件。在另一个层间绝缘膜中，形成电耦合到磁阻元件的位线。在磁阻电阻元件的正下方形成数位线。

12. 发明授权

US08084343B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08084343B2
公开(公告)日：2011-12-27
申请号：US12977573
申请日：2010-12-23
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/20
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
摘要翻译：为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜，层间绝缘膜。

13. 发明申请

US20110092037A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110092037A1
公开(公告)日：2011-04-21
申请号：US12977573
申请日：2010-12-23
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/336
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
摘要翻译：为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜，层间绝缘膜。

14. 发明申请

US20090289367A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090289367A1
公开(公告)日：2009-11-26
申请号：US12472100
申请日：2009-05-26
申请人： Daisuke KODAMA , Shoichi Fukui , Hiroshi Miyazaki , Tatsunori Murata
发明人： Daisuke KODAMA , Shoichi Fukui , Hiroshi Miyazaki , Tatsunori Murata
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/3148 , H01L21/318 , H01L21/76832 , H01L23/53295 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnection layer is formed in an interconnection trench at a surface of an interlayer insulating film. A diffusion preventing insulating film is formed to cover the copper interconnection layer and is made of at least one of SiC and SiCN. An insulating film is formed on the copper interconnection layer with the diffusion preventing insulating film interposed and is made of SiN.
摘要翻译：在层间绝缘膜的表面的互连沟槽中形成铜互连层。形成扩散防止绝缘膜以覆盖铜互连层，并且由SiC和SiCN中的至少一种制成。在铜互连层上形成有绝缘膜，其中扩散防止绝缘膜插入并由SiN制成。

15. 发明申请

US20070111512A1 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070111512A1
公开(公告)日：2007-05-17
申请号：US11651095
申请日：2007-01-09
申请人： Tatsunori Murata , Takahiro Nakamura , Yasumichi Suzuki
发明人： Tatsunori Murata , Takahiro Nakamura , Yasumichi Suzuki
IPC分类号： H01L21/4763
CPC分类号： H01L27/11 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L29/66666 , H01L29/7827
摘要： For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (03-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.
摘要翻译：为了改善构成SRAM存储单元的垂直MISFET之间的归档特性，垂直MISFET形成在水平驱动MISFET和转移MISFET之上，它们在Y方向上以窄间距设置，在X方向上具有宽间距。在具有较低覆盖度的第一绝缘膜（0 3 3 -TEOS）之后，在具有下半导体层，中间半导体层，上半导体层和氮化硅膜和栅电极通过栅极绝缘膜形成在层叠体的侧壁上以完全填充窄的间距空间，第二绝缘膜（HDP氧化硅膜）沉积在第一绝缘膜上，导致填充性能的改善，即使在窄间距部分，具有高纵横比的垂直MISFET之间。

16. 发明授权

US08685854B2 Method of forming a via in a semiconductor device 有权
标题翻译：在半导体器件中形成通孔的方法
公开(公告)号：US08685854B2
公开(公告)日：2014-04-01
申请号：US13046331
申请日：2011-03-11
申请人： Kazuhito Ichinose , Kotaro Kihara , Tatsunori Murata
发明人： Kazuhito Ichinose , Kotaro Kihara , Tatsunori Murata
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/76831 , H01L23/481 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
摘要翻译：将钨构件埋入形成在要形成盲孔贯通孔的晶片中的盲孔中的工序。在晶片周围进行成膜（用于形成钨构件），在钨膜下方的阻挡金属的外周的钨构件的外周部位置。该方法使得可以将可能相对较薄的钨构件埋入可能相对较大的盲孔中，以减少晶片的翘曲，并进一步防止钨构件下方的下层被剥离在晶片的周边。

17. 发明申请

US20110049657A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110049657A1
公开(公告)日：2011-03-03
申请号：US12870486
申请日：2010-08-27
申请人： Keisuke TSUKAMOTO , Shinya Hirano , Yuichiro Fujiyama , Tatsunori Murata
发明人： Keisuke TSUKAMOTO , Shinya Hirano , Yuichiro Fujiyama , Tatsunori Murata
IPC分类号： H01L29/82 , H01L21/18
CPC分类号： H01L27/105 , H01L27/228 , H01L43/08 , H01L43/12
摘要： There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.
摘要翻译：提供一种半导体器件，其中减小了电阻元件等中的短路故障及其制造方法。其中形成存储单元的层间绝缘膜形成为使得位于形成有磁阻元件的存储单元区域中的层间绝缘膜的部分的上表面位于比上表面的位置低的位置层间绝缘膜的位于周边区域的部分。形成另一层间绝缘膜以覆盖磁阻元件。在另一个层间绝缘膜中，形成电耦合到磁阻元件的位线。在磁阻电阻元件的正下方形成数位线。

18. 发明授权

US07875539B2 Semiconductor device 有权
公开(公告)号：US07875539B2
公开(公告)日：2011-01-25
申请号：US12234079
申请日：2008-09-19
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/20
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

19. 发明授权

US07759722B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759722B2
公开(公告)日：2010-07-20
申请号：US11765703
申请日：2007-06-20
申请人： Tatsunori Murata , Koyu Asai , Hiroaki Iuchi
发明人： Tatsunori Murata , Koyu Asai , Hiroaki Iuchi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/7682 , H01L21/76834 , H01L27/11521 , H01L27/14627 , H01L27/14632 , H01L27/14643 , H01L27/14689 , H01L29/42324
摘要： When microfabrication is done, a reliable semiconductor device is offered.A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.
摘要翻译：当进行微细加工时，提供可靠的半导体器件。半导体器件具有半导体衬底，该半导体衬底具有主前表面，多个凸形图案形成在半导体衬底的主表面上，以便可以具有浮置栅极和控制栅极，第一绝缘膜形成为使得可以覆盖多个凸形图案中的每一个的上表面和侧表面，并且使得宽度可能变大，而不是覆盖覆盖上部侧表面的部分中的凸形图案的下部侧表面的部分以及覆盖第一绝缘膜的上表面和侧表面的第二绝缘膜，使得相邻凸形图案之间的空腔可能被遮挡。由空腔的第二绝缘膜封闭的位置是比浮动栅极的上表面高的位置，并且是比控制栅极的上表面低的位置。

20. 发明授权

US07482650B2 Method of manufacturing a semiconductor integrated circuit device having a columnar laminate 失效
标题翻译：制造具有柱状层压体的半导体集成电路器件的方法
公开(公告)号：US07482650B2
公开(公告)日：2009-01-27
申请号：US11936370
申请日：2007-11-07
申请人： Tatsunori Murata , Takahiro Nakamura , Yasumichi Suzuki
发明人： Tatsunori Murata , Takahiro Nakamura , Yasumichi Suzuki
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L29/66666 , H01L29/7827
摘要： For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over a columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.
摘要翻译：为了改善构成SRAM存储单元的垂直MISFET之间的填充特性，垂直MISFET形成在水平驱动MISFET和转移MISFET之上，它们在Y方向上以窄间距设置，在X方向上具有宽间距。在具有良好覆盖率的第一绝缘膜（O3-TEOS）设置在具有下半导体层，中间半导体层，上半导体层和氮化硅膜的柱状层压体上，以及形成在通过栅极绝缘膜层叠以完全填充窄的间距空间，在第一绝缘膜上沉积第二绝缘膜（HDP氧化硅膜），导致即使在窄间距部分之间，垂直具有高纵横比的MISFET。

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