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11. 发明授权

US08951832B2 Variable-resistance material memories and methods 有权
标题翻译：可变电阻材料存储器和方法
公开(公告)号：US08951832B2
公开(公告)日：2015-02-10
申请号：US14216068
申请日：2014-03-17
申请人： Micron Technology, Inc.
发明人： Jun Liu
IPC分类号： H01L21/06 , H01L21/82 , H01L45/00 , H01L27/10 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/101 , H01L27/24 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/1253 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , H01L45/1691
摘要： Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
摘要翻译：可变电阻存储材料单元由垂直底部间隔电极接触。可变电阻材料存储器间隔体通过电极沿边缘接触。工艺包括形成底部间隔电极以及可变电阻材料存储器隔离单元。器件包括可变电阻存储单元。

12. 发明授权

US08846442B2 Method for producing semiconductor layers and coated substrates treated with elemental selenium and/or sulphur, in particular flat substrates 有权
标题翻译：用元素硒和/或硫处理的半导体层和涂覆基底的制造方法，特别是平坦的基底
公开(公告)号：US08846442B2
公开(公告)日：2014-09-30
申请号：US13131802
申请日：2009-11-30
申请人： Volker Probst
发明人： Volker Probst
IPC分类号： H01L21/06
CPC分类号： H01L21/67109 , C23C14/5866 , C23C16/4411 , H01L21/02568 , H01L21/67005 , H01L21/67017 , H01L21/67098 , H01L31/0322 , H01L31/20 , Y02E10/541 , Y02P70/521
摘要： The invention relates to a method for producing semiconductor layers and coated substrates treated with elemental selenium and/or sulphur, in particular flat substrates, containing at least one conducting, semiconducting and/or insulating layer, in which a substrate which is provided with at least one metal layer and/or with at least one layer containing metal, in particular a stack of substrates, each of which is provided with at least one metal layer and/or with at least one layer which contains metal, is inserted into a processing chamber and heated to a predetermined substrate temperature; elementary selenium and/or sulphur vapor is guided past on the or on every metal layer and/or layer containing metal, from a source located inside and/or outside the processing chamber, in particular by means of a carrier gas which is in particular inert, under rough vacuum conditions or ambient pressure conditions or overpressure conditions, in order to react chemically with said layer with selenium or sulphur in a targeted manner; the substrate is heated by means of forced convection by at least one gas conveying device and/or the elementary selenium and/or sulphur vapor is mixed and guided past on the substrate by means of forced convection by at least one gas conveying device in the processing chamber, in particular in a homogeneous manner. The invention furthermore relates to a processing device for implementing a method of this type.
摘要翻译：本发明涉及用元素硒和/或硫处理的半导体层和涂覆衬底的方法，特别是含有至少一个导电，半导体和/或绝缘层的平坦衬底，其中衬底至少被提供至少一个金属层和/或至少一层含有金属的层，特别是一层衬底，其中每个衬底设置有至少一个金属层和/或至少一层含有金属的层，被插入处理室并加热到预定的基板温度; 基本硒和/或硫蒸气从位于处理室内部和/或处于处理室内部的源引导到每个金属层和/或含有金属的层上或之上，特别是通过载气特别是惰性的在粗糙真空条件或环境压力条件或超压条件下，以目标方式与所述层与硒或硫化学反应; 通过至少一个气体输送装置的强制对流来加热基底，和/或基本硒和/或硫蒸气在加工过程中通过至少一个气体输送装置的强制对流被混合和引导通过基底特别是以均匀的方式。本发明还涉及一种用于实现这种方法的处理装置。

13. 发明授权

US08796661B2 Nonvolatile memory cells and methods of forming nonvolatile memory cell 有权
标题翻译：非易失性存储单元和形成非易失性存储单元的方法
公开(公告)号：US08796661B2
公开(公告)日：2014-08-05
申请号：US12917348
申请日：2010-11-01
申请人： Nirmal Ramaswamy , Gurtej Sandhu
发明人： Nirmal Ramaswamy , Gurtej Sandhu
IPC分类号： H01L47/00 , H01L21/06 , H01L21/20
CPC分类号： H01L45/085 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683
摘要： A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.
摘要翻译：形成非易失性存储单元的方法包括形成具有第一电流导电材料的第一电极和从第一电流导电材料向外突出的周向自对准的第二导电材料。第二电流导电材料的组成不同于第一电流导电材料。可编程区域形成在第一电流导电材料之上并且在第一电极的突出的第二电流导电材料之上。在可编程区域上形成第二电极。在一个实施例中，可编程区域是离子传导材料，并且第一和第二电极中的至少一个电极具有直接抵靠离子导电材料的电化学活性表面。公开了其它方法和结构方面。

14. 发明授权

US08735214B2 Method for the preparation of group IB-IIIA-VIA quaternary or higher alloy semiconductor films 有权
标题翻译： IB-IIIA-VIA族四元以上合金半导体膜的制备方法
公开(公告)号：US08735214B2
公开(公告)日：2014-05-27
申请号：US12728054
申请日：2010-03-19
申请人： Vivian Alberts
发明人： Vivian Alberts
IPC分类号： H01L21/06
CPC分类号： H01L31/0322 , H01L31/18 , Y02E10/541 , Y02P70/521
摘要： This invention relates to a method for producing group IB-IIIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VIA1 ternary alloy of step (ii); (iv) heat treating either the first film or second film to form a group IB-IIIA-VIA quaternary or higher alloy semiconductor film.
摘要翻译：本发明涉及生产IB-IIIA-VIA族或更高合金半导体膜的方法，其中该方法包括以下步骤：（i）提供包含IB族和IIIA族金属的混合物的金属膜; （ii）在条件下在第一组VIA元件（所述第一组VIA元件在下文中称为VIA1）的源的存在下对金属膜进行热处理，以形成第一膜，所述第一膜包含至少一种二元合金的混合物，所述二元合金选自来自由IB-VIA1族合金和IIIA-VIA1族合金组成的组和至少一种IB-IIIA-VIA1族三元合金组合（iii）任选地在第二组源的存在下热处理第一膜VIA 元素（所述第二族VI元素以下称为VIA2）在将第一膜转化为第二膜的条件下，所述第二膜包含选自由IB-VIA1-VIA2族合金和IIIA-VIA1族组成的组中的至少一种合金 -VIA2合金; 和步骤（ii）的至少一种IB-III-VIA1族三元合金; （iv）热处理第一膜或第二膜以形成IB-IIIA-VIA族或更高合金半导体膜。

15. 发明授权

US08722455B2 Phase change memory structure having low-K dielectric heat-insulating material and fabrication method thereof 有权
标题翻译：具有低K介电隔热材料的相变存储结构及其制造方法
公开(公告)号：US08722455B2
公开(公告)日：2014-05-13
申请号：US13202955
申请日：2011-06-24
申请人： Zhitang Song , Liangcai Wu , Songlin Feng
发明人： Zhitang Song , Liangcai Wu , Songlin Feng
IPC分类号： H01L21/06 , H01L21/20 , H01L21/8258 , H01L29/792
CPC分类号： H01L21/8258 , H01L27/2409 , H01L29/7923 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： The present invention discloses a phase change memory structure having low-k dielectric heat-insulating material and fabrication method thereof, wherein the phase change memory cell comprises diode, heating electrode, reversible phase change resistor, top electrode and etc; the heating electrode and reversible phase change resistor are surrounded by low-k dielectric heat-insulating layer; an anti-diffusion dielectric layer is designed between the reversible phase change resistor and the low-k dielectric heat-insulating layer surrounding thereof. The present invention utilizes low-k dielectric material as heat-insulating material, thereby avoiding thermal crosstalk and mutual influence during operation between phase change memory cells, enhancing the reliability of devices, and eliminating the influence of temperature, pressure and etc. on phase change random access memory (PCRAM) data retention during the change from amorphous to polycrystalline states. Furthermore, an anti-diffusion dielectric layer is prepared between the low-k dielectric material and the phase change material, which can be used to prevent the elements of the phase change material from diffusing to low-k dielectric material. The fabrication process of said phase change memory is compatible with standard complementary metal-oxide semiconductor (CMOS) process and the chemical mechanical polishing (CMP) process with low pressure and light corrosion is adopted in polishing.
摘要翻译：本发明公开了一种具有低k介电绝缘材料的相变存储器结构及其制造方法，其中相变存储单元包括二极管，加热电极，可逆相变电阻器，顶电极等; 加热电极和可逆相变电阻器被低k电介质绝热层包围; 在可逆相变电阻器和围绕其的低k电介质隔热层之间设计了抗扩散电介质层。本发明利用低k绝缘材料作为绝热材料，从而避免相变存储器单元之间的热串扰和相互影响，提高器件的可靠性，消除温度，压力等对相变的影响随机存取存储器（PCRAM）在从无定形到多晶状态的变化期间的数据保留。此外，在低k电介质材料和相变材料之间制备抗扩散电介质层，其可用于防止相变材料的元素扩散到低k电介质材料。所述相变存储器的制造过程与标准互补金属氧化物半导体（CMOS）工艺兼容，并且在抛光中采用具有低压和轻腐蚀的化学机械抛光（CMP）工艺。

16. 发明授权

US08470719B2 Method for fabricating phase change memory device using solid state reaction 有权
标题翻译：使用固态反应制造相变存储器件的方法
公开(公告)号：US08470719B2
公开(公告)日：2013-06-25
申请号：US13110579
申请日：2011-05-18
申请人： Seung Yun Lee , Young Sam Park , Sung Min Yoon , Soon Won Jung , Byoung Gon Yu
发明人： Seung Yun Lee , Young Sam Park , Sung Min Yoon , Soon Won Jung , Byoung Gon Yu
IPC分类号： H01L21/461 , H01L21/06
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1666
摘要： Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.
摘要翻译：提供了一种非易失性存储器件及其制造方法，其中使用固态反应形成相变层以减少可编程体积，从而降低功耗。该装置包括第一反应物层，形成在第一反应物层上的第二反应物层和由形成第一反应物层的材料与第一反应物层之间的固态反应形成在第一和第二反应物层之间的相变层形成第二反应物层的材料。相变存储器件消耗低功率并以高速运行。

17. 发明授权

US08440535B2 Forming a phase change memory with an ovonic threshold switch 有权
标题翻译：形成一个带有超声门限开关的相变存储器
公开(公告)号：US08440535B2
公开(公告)日：2013-05-14
申请号：US13463072
申请日：2012-05-03
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/20 , H01L21/00 , H01L21/06
CPC分类号： H01L45/144 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/1675
摘要： A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
摘要翻译：相变存储器可以包括在氰色存储器上形成的超声阈值开关。在一个实施例中，开关包括与下面的电极重叠的硫族化物层。然后，由于蚀刻硫族化物层而导致的边缘损坏可以被隔离以减少漏电流。

18. 发明授权

US08426242B2 Composite target sputtering for forming doped phase change materials 有权
标题翻译：用于形成掺杂相变材料的复合靶溅射
公开(公告)号：US08426242B2
公开(公告)日：2013-04-23
申请号：US13076169
申请日：2011-03-30
申请人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
发明人： Huai-Yu Cheng , Chieh-Fang Chen , Hsiang-Lan Lung , Yen-Hao Shih , Simone Raoux , Matthew J. Breitwisch
IPC分类号： H01L21/06
CPC分类号： H01L47/00 , C23C14/06 , C23C14/0623 , C23C14/3414 , H01L21/06 , H01L27/24 , H01L45/144 , H01L45/1625
摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.
摘要翻译：使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

19. 发明授权

US08372688B2 Method for forming Ge-Sb-Te film and storage medium 有权
标题翻译： Ge-Sb-Te薄膜和储存介质的形成方法
公开(公告)号：US08372688B2
公开(公告)日：2013-02-12
申请号：US13376749
申请日：2010-06-02
申请人： Yumiko Kawano , Susumu Arima
发明人： Yumiko Kawano , Susumu Arima
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , C23C16/02 , C23C16/305 , C23C16/4405 , H01L45/144 , H01L45/1616
摘要： A film-forming method includes a preprocessing step (step 1) wherein the inside of a processing chamber is exposed to a gas containing Cl and/or F in a state having no substrate in the processing chamber, and a step (step 2) wherein a substrate is loaded into the processing chamber after the step 1. Then, in a step 3, a gaseous Ge raw material, a gaseous Sb raw material, and a gaseous Te raw material are introduced into the processing chamber having the substrate loaded therein, and a Ge—Sb—Te film formed of Ge2Sb2Te5 is formed on the substrate by CVD.
摘要翻译：成膜方法包括在处理室内没有基板的状态下将处理室的内部暴露于含有Cl和/或F的气体的预处理步骤（步骤1）和步骤（步骤2），其中在步骤1之后将基板装载到处理室中。然后，在步骤3中，将气态Ge原料，气态Sb原料和气态Te原料引入到其中装载有基板的处理室中，并且通过CVD在基板上形成由Ge 2 Sb 2 Te 5形成的Ge-Sb-Te膜。

20. 发明授权

US08372687B2 System, method and apparatus for forming multiple layers in a single process chamber 有权
标题翻译：用于在单个处理室中形成多个层的系统，方法和装置
公开(公告)号：US08372687B2
公开(公告)日：2013-02-12
申请号：US12932114
申请日：2011-02-16
申请人： Aiguo Feng
发明人： Aiguo Feng
IPC分类号： H01L21/06 , H01L21/00 , H01L21/36 , H01L29/08
CPC分类号： H01L31/0322 , C23C14/5866 , H01L21/0237 , H01L21/02568 , H01L21/02614 , Y02E10/541 , Y02P70/521
摘要： A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed.
摘要翻译：在单个处理室中形成多层的方法包括将衬底放置在具有多个处理源的处理室中并且迭代地形成铜铟镓硒（CIGS），其包括形成多个相对较薄的CIGS层，包括形成铜铟镓（CIG）所述CIG层具有小于约50埃至约200埃的厚度，在所述CIG层上形成硒层，所述硒层具有介于小于约50埃至约200埃之间的厚度，以及加热基底，CIG层和硒层。还公开了一种处理室系统。

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