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1. 发明授权

US10886451B2 Thermoelectric material, method of fabricating the same, and thermoelectric device 有权
公开(公告)号：US10886451B2
公开(公告)日：2021-01-05
申请号：US15536268
申请日：2017-03-09
申请人： UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITY
发明人： Mann Ho Cho , Hye Jin Choi , Ji Min Chae , Han Bum Park
IPC分类号： H01L35/26 , H01L35/16 , H01L35/34 , H01L35/32 , H01L27/16 , H01L35/00 , H01L21/06 , H01L35/18 , H01L35/02 , H01L35/12
摘要： Provided are a thermoelectric material, a method of fabricating the same, and a thermoelectric device. The thermoelectric material includes a first material layer including a chalcogen element; and a second material layer including a reaction compound between the chalcogen element and a metal element, wherein the thermoelectric material has a structure in which the first material layer is inserted in the second material layer.

2. 发明申请

US20180282150A1 HIERARCHICAL MICRO ASSEMBLER SYSTEM 审中-公开
公开(公告)号：US20180282150A1
公开(公告)日：2018-10-04
申请号：US15476830
申请日：2017-03-31
申请人： Palo Alto Research Center Incorporated
发明人： Jeng Ping Lu , Eugene M. Chow , David K. Biegelsen , Sourobh Raychaudhuri
IPC分类号： B81C1/00 , B82Y30/00 , B82Y40/00 , H01L21/027 , H01L21/06 , H01L29/06 , H01L31/0236 , H01L31/0352
CPC分类号： H01L29/0665 , B01J2219/00648 , B01J2219/00653 , B01J2219/00659 , B81B2203/04 , B81B2207/056 , B81C3/005 , B81C2201/0149 , B82Y30/00 , B82Y40/00 , H01L21/06 , H01L24/06 , H01L31/0352 , Y02E10/50
摘要： An electrode array including a substrate. The electrode array includes a first plurality of electrodes disposed above a first zone of the substrate, wherein the first plurality of electrodes has a first range of spacing. The electrode array further includes a second plurality of electrodes disposed above a second zone of the substrate, wherein the second plurality of electrodes has a second range of spacing that is less than the first range of spacing.

3. 发明授权

US09837269B2 Deposition method for planar surfaces 有权
公开(公告)号：US09837269B2
公开(公告)日：2017-12-05
申请号：US14956173
申请日：2015-12-01
申请人： HGST, Inc.
发明人： Mac D. Apodaca
IPC分类号： H01L21/06 , H01L21/02 , H01L29/26
CPC分类号： H01L21/02568 , H01L21/02381 , H01L21/02485 , H01L21/02494 , H01L29/26
摘要： A method for producing a substantially planar surface for semiconductor processing to improve lithography, planarization, and other process steps that benefit from a flat substrate. The method includes depositing a first alloy to form a first layer on a substrate. The first layer has a center high deposition, meaning the height in the center of the substrate is higher than the height at the edges of the substrate. The method further includes depositing a second alloy on the first layer to form a second layer. The first alloy has a different composition than the second alloy. In such a method the net deposition is substantially planar reducing or eliminating deposition induced long-range distortions that might occur across a substrate.

4. 发明授权

US09831422B2 Magnetic memory devices having perpendicular magnetic tunnel junction 有权
公开(公告)号：US09831422B2
公开(公告)日：2017-11-28
申请号：US14919717
申请日：2015-10-21
申请人： Samsung Electronics Co., Ltd. , International Business Machines Corporation
发明人： Woojin Kim , Joonmyoung Lee , Yong Sung Park , Stuart S. P. Parkin
IPC分类号： H01L29/82 , H01L21/06 , H01L43/08 , H01L43/02
CPC分类号： H01L43/08 , H01L43/02 , H01L43/10
摘要： A magnetic memory device includes a first magnetic structure on a substrate, a second magnetic structure between the substrate and the first magnetic structure, and a tunnel barrier between the first and second magnetic structures. At least one of the first and second magnetic structures includes a perpendicular magnetic layer on the tunnel barrier, and a polarization enhancement layer interposed between the tunnel barrier and the perpendicular magnetic layer. Here, the polarization enhancement layer contains cobalt, iron, and at least one of the elements of Group IV, and the polarization enhancement layer has a magnetization direction perpendicular to or substantially perpendicular to a top surface of the substrate.

5. 发明授权

US09768072B1 Fabrication of a vertical fin field effect transistor with reduced dimensional variations 有权
公开(公告)号：US09768072B1
公开(公告)日：2017-09-19
申请号：US15199352
申请日：2016-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng
IPC分类号： H01L21/06 , H01L29/06 , H01L21/8234 , H01L21/02 , H01L21/308 , H01L27/088 , H01L21/3065 , H01L27/108 , H01L27/11
CPC分类号： H01L21/823487 , H01L21/02532 , H01L21/02598 , H01L21/266 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/823412 , H01L21/823431 , H01L21/823481 , H01L27/088 , H01L27/10826 , H01L27/1104 , H01L29/0603 , H01L29/66666 , H01L29/66795
摘要： A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

6. 发明授权

US09373788B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09373788B2
公开(公告)日：2016-06-21
申请号：US14185427
申请日：2014-02-20
申请人： SK hynix Inc.
发明人： Young Seok Kwon , Kwon Hong
IPC分类号： H01L21/06 , H01L45/00 , C23C16/30 , C23C16/455
CPC分类号： H01L45/1616 , C23C16/305 , C23C16/45523 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (Ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form Ge elements on the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法包括：将包含锗（Ge）前体的第一源气体在第一时间段内提供到半导体衬底上，并且周期性地中断第一时间段内的第一源气体的供应以形成Ge元素半导体衬底。

7. 发明授权

US09231203B1 Doped narrow band gap nitrides for embedded resistors of resistive random access memory cells 有权
标题翻译：用于电阻随机存取存储器单元的嵌入式电阻器的掺杂窄带隙氮化物
公开(公告)号：US09231203B1
公开(公告)日：2016-01-05
申请号：US14565097
申请日：2014-12-09
申请人： Intermolecular Inc.
发明人： Mihir Tendulkar , Milind Weling
IPC分类号： H01L21/06 , H01L47/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L45/00
CPC分类号： H01L45/145 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.
摘要翻译：提供了存储单元，例如电阻随机存取存储器（ReRAM）单元，以及制造这样的单元的方法。单元包括在嵌入式电阻器内串联连接的嵌入式电阻器和电阻开关层。嵌入式电阻器可防止电阻开关层过多的电流，特别是当电阻式开关层切换到低电阻状态时。嵌入式电阻器包括具有小于2eV的带隙的化学计量氮化物。嵌入式电阻器被配置为在电池的整个制造和操作过程中保持基本恒定的电阻，例如退火电池并使电池成形和切换信号。化学计量氮化物可以是氮化铪，氮化锆或氮化钛之一。嵌入式电阻器还可以包括掺杂剂，例如钽，铌，钒，钨，钼或铬。

8. 发明授权

US09203024B2 Copper compatible chalcogenide phase change memory with adjustable threshold voltage 有权
公开(公告)号：US09203024B2
公开(公告)日：2015-12-01
申请号：US11881080
申请日：2007-07-25
申请人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
发明人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
IPC分类号： H01L21/00 , H01L21/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/144 , H01L27/24 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer.

9. 发明授权

US09006022B2 Method for fabricating phase change memory 有权
标题翻译：制造相变存储器的方法
公开(公告)号：US09006022B2
公开(公告)日：2015-04-14
申请号：US14056253
申请日：2013-10-17
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Ying Li , Neil Zhu , Guanping Wu
IPC分类号： H01L21/06 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/144 , H01L45/1683
摘要： A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.
摘要翻译：提供了一种用于制造相变存储器的方法。该方法包括提供具有与一个或多个半导体器件连接的底部电极并在半导体衬底上形成第一电介质层的半导体衬底。该方法还包括在第一电介质层中形成环形电极，以及形成具有暴露第一电介质层的一部分和环形电极的一部分的第一开口的第二电介质层。此外，该方法包括在第二电介质层的第一开口中形成相变层，使得可以控制相变层和环形电极之间的接触面积以实现期望的接触，并形成顶部电极。

10. 发明授权

US08987045B2 Methods of forming a memory device 有权
标题翻译：形成存储器件的方法
公开(公告)号：US08987045B2
公开(公告)日：2015-03-24
申请号：US13369507
申请日：2012-02-09
申请人： Jun Liu
发明人： Jun Liu
IPC分类号： H01L21/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.
摘要翻译：具有多个存储单元的存储器件，每个存储单元包括具有横向收缩部分的相变材料。相邻存储单元的横向收缩部分垂直偏移并且位于存储器件的相对侧上。还公开了具有多个存储单元的存储器件，每个存储器单元包括具有不同宽度的第一和第二电极。相邻存储器单元具有在存储器件的垂直相对侧上偏移的第一和第二电极。还公开了形成存储器件的方法。

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