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11. 发明申请

US20210367563A1 SYSTEMS AND METHODS FOR TIA BASE CURRENT DETECTION AND COMPENSATION 有权
公开(公告)号：US20210367563A1
公开(公告)日：2021-11-25
申请号：US17392062
申请日：2021-08-02
申请人： VELODYNE LIDAR USA, INC.
发明人： Roger Pinto , Pravin Kumar Venkatesan
IPC分类号： H03F1/30 , H03G3/00 , H03F3/343 , H03G3/30 , H03M1/74
摘要： Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip.

12. 发明授权

US11144316B1 Current-mode mixed-signal SRAM based compute-in-memory for low power machine learning 有权
公开(公告)号：US11144316B1
公开(公告)日：2021-10-12
申请号：US16997229
申请日：2020-08-19
申请人： Ali Tasdighi Far
发明人： Ali Tasdighi Far
IPC分类号： H03M1/10 , G06F9/30 , G06F13/40 , H03M1/74 , G11C11/412 , G06N20/00
摘要： Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, and MACs. Typically, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, and MACs increase, usually the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications. Moreover, the multipliers and MACs disclosed in this invention can be placed near conventional CMOS memory cells, such as Static-Random-Access-Memory (SRAM) or Electrically Programmable Read-Only Memory (EPROM) or Electrically Erasable Programmable Read-Only Memory (E2PROM), which facilitates In-Memory-Compute (IMC) and or near-memory-compute (NMC), that can further reduce dynamic power consumption.

13. 发明申请

US20210266009A1 OPTICAL COMMUNICATION APPARATUS AND CORRECTING METHOD 有权
公开(公告)号：US20210266009A1
公开(公告)日：2021-08-26
申请号：US17163900
申请日：2021-02-01
申请人： Fujitsu Optical Components Limited
发明人： TOSHIO ISHII
IPC分类号： H03M3/00 , H03H17/06 , H03M1/74
摘要： An optical communication apparatus includes a level detector, an FIR filter, and a adjustor. The level detector detects level information that discriminates a change in a multi-value level based on an input signal used in a multi-value amplitude modulation system. The FIR filter compensates a signal band of the input signal in accordance with tap coefficients of a plurality of multipliers. The adjustor corrects the tap coefficient of each of the multipliers included in the FIR filter based on the level information detected in the level detector.

14. 发明申请

US20210175894A1 CURRENT DIGITAL-TO-ANALOG CONVERTER WITH WARMING OF DIGITAL-TO-ANALOG CONVERTER ELEMENTS 有权
公开(公告)号：US20210175894A1
公开(公告)日：2021-06-10
申请号：US16942062
申请日：2020-07-29
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： John L. MELANSON , Johann G. GABORIAU , Lei Zhu , Wai-Shun Shum , Xiaofan Fei , Leyi Yin
IPC分类号： H03M1/74 , H03M3/00 , H04R3/00
摘要： A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

15. 发明授权

US11031948B1 Diagnostic system 有权
公开(公告)号：US11031948B1
公开(公告)日：2021-06-08
申请号：US17034738
申请日：2020-09-28
申请人： Baker Hughes Oilfield Operations LLC
发明人： Lifeng Wang , Hao Wang , Zhili Zhou , Xiaoyan Huang , Ran Ao
IPC分类号： H03M1/68 , H03M1/74 , H03M1/70
摘要： A diagnostic system includes a detection circuit comprising a first impedance, a second impedance, a first input pin, a second input pin, a first output pin and a second output pin. The detection circuit is configured to receive an input signal via the first and the second input pins. The first impedance is configured to electrically couple the first input pin and the first output pin, and the second impedance is configured to electrically couple the first input pin with the second input pin and second output pin. The diagnostic system also includes a communication channel. The diagnostic system further includes an input circuit comprising a third input pin, a fourth input pin and a third output pin. The input circuit is configured to provide, via the third output pin, a voltage signal.

16. 发明授权

US11005569B1 Optical transmitter having cascaded modulators 有权
公开(公告)号：US11005569B1
公开(公告)日：2021-05-11
申请号：US17005391
申请日：2020-08-28
申请人： Nokia Solutions and Networks OY
发明人： Joon Ho Cho , Xi Chen
IPC分类号： H04B10/516 , H04Q11/00 , H04B10/25 , H04B10/50 , H03M1/74
摘要： An optical data transmitter comprising two or more serially connected optical modulators, each driven using a respective DAC. The digital signals applied to the individual DACs are produced using different respective subsets of the set of bitstreams representing the digital waveform or data stream to be transmitted, with the bitstream subsets being selected, e.g., such that (i) each of the individual DACs is able to support the digital resolution and sampling rate needed for properly handling the subset of bitstreams applied thereto and (ii) differences between average driving powers applied to different optical modulators are relatively small. In different embodiments, the two or more serially connected optical modulators can be arranged for generating optical communication signals of different modulation formats, e.g., PSK, ASK, PAM, IM, and QAM. Some embodiments can advantageously be used for generating optical communication signals employing constellations of relatively large sizes, e.g., larger than 1000 symbols.

17. 发明授权

US10985768B2 Ultra-high speed digital-to-analog (DAC) conversion methods and apparatus having sub-DAC systems for data interleaving and power combiner with no interleaving 有权
公开(公告)号：US10985768B2
公开(公告)日：2021-04-20
申请号：US16990905
申请日：2020-08-11
申请人： Jariet Technologies, Inc.
发明人： Ark-Chew Wong , Richard Dennis Alexander , Craig A. Hornbuckle
IPC分类号： H03M1/66 , H03M1/06 , H03M1/00 , H03M1/74
摘要： A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

18. 发明授权

US10972062B2 Class-D amplifier and method 有权
公开(公告)号：US10972062B2
公开(公告)日：2021-04-06
申请号：US16776030
申请日：2020-01-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03F3/217 , H03F3/183 , H03M1/12 , H03M3/00 , H02M1/12 , H03M1/74
摘要： A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal.

19. 发明授权

US10938406B2 Membrane digital analog switches 有权
公开(公告)号：US10938406B2
公开(公告)日：2021-03-02
申请号：US16724910
申请日：2019-12-23
申请人： Cattron North America, Inc.
发明人： David Stagg , Thomas Hornung , Ryan Wooten
IPC分类号： H03M11/00 , H03M1/74 , G01L1/00 , H03M1/36
摘要： A membrane digital analog switch includes an input button surface adapted to receive an input pressure from a user, and a digital switch positioned below the input button surface to generate a digital switch activation signal when the received pressure on the input button surface is greater than or equal to a specified digital pressure threshold. The membrane digital analog switch also includes an analog switch adapted to generate an analog switch activation signal when the received pressure on the input button surface is greater than or equal to a specified analog pressure threshold. The specified analog pressure threshold is greater than the specified digital pressure threshold, the digital switch activation signal is a binary digital signal, and the analog switch activation signal is variable and corresponds to an analog sensed value of the received pressure on the input button surface.

20. 发明授权

US10857567B2 Analog to digital signal conversion in ultrasound device 有权
公开(公告)号：US10857567B2
公开(公告)日：2020-12-08
申请号：US16011776
申请日：2018-06-19
申请人： Butterfly Network, Inc.
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
IPC分类号： G01S7/53 , G01S7/524 , G01S15/89 , B06B1/02 , H03M3/00 , B06B1/06 , H03M1/74
摘要： An ultrasound device is describe in which analog ultrasonic transducer output signal are directly converted to digital signals. The ultrasound device includes microfabricated ultrasonic transducers directly coupled to a sigma delta analog-to-digital converter in some instances. The direct digital conversion may allow for omission of undesirable analog processing stages in the ultrasound circuitry chain. In some situations, the ADC may be integrated on the same substrate as the ultrasound transducer.

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