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11. 发明授权

US09640553B2 Thin-film transistor (TFT), manufacturing method thereof, array substrate and display device 有权
公开(公告)号：US09640553B2
公开(公告)日：2017-05-02
申请号：US14762076
申请日：2014-11-21
申请人： BOE Technology Group Co., Ltd.
发明人： Chunsheng Jiang
IPC分类号： H01L21/20 , H01L21/36 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1214 , H01L27/1259 , H01L29/42384 , H01L29/4908 , H01L29/66969 , H01L29/786 , H01L29/7869 , H01L2029/42388
摘要： A thin-film transistor (TFT), a manufacturing method thereof, an array substrate and a display device are disclosed. The method for manufacturing the a TFT comprises the step of forming a gate electrode, a gate insulating layer, an active area, a source electrode and a drain electrode on a base substrate. The active area (4) is made of a ZnON material. When the gate insulating layer is formed, a material for forming the gate insulating layer is subjected to control treatment, so that a sub-threshold amplitude of the TFT is less than or equal to 0.5 mV/dec. The manufacturing method reduces the sub-threshold amplitude of the TFT and improves the semiconductor characteristic of the TFT.

12. 发明授权

US09627490B1 Epitaxial growth of high quality vanadium dioxide films with template engineering 有权
公开(公告)号：US09627490B1
公开(公告)日：2017-04-18
申请号：US14974178
申请日：2015-12-18
申请人： Wisconsin Alumni Research Foundation
发明人： Chang-Beom Eom , Daesu Lee
IPC分类号： H01L29/24 , H01L21/02 , H01L21/36 , H03K17/56 , H01L29/78 , H01L29/66 , H01L29/10 , H03K17/687 , H01L45/00 , H03K17/51
CPC分类号： H01L29/24 , H01L21/02414 , H01L21/02483 , H01L21/02488 , H01L21/02513 , H01L21/02565 , H01L21/02631 , H01L29/1033 , H01L29/1079 , H01L29/66969 , H01L29/78 , H01L29/7869 , H01L45/065 , H01L45/1206 , H01L45/146 , H03K17/04 , H03K17/51 , H03K17/687
摘要： Layered oxide structures comprising an overlayer of high quality VO2 and methods of fabricating the layered oxide structures are provided. Also provided are high-speed switches comprising the layered structures and methods of operating the high-speed switches. The layered oxide structures include high quality VO2 epitaxial films on isostructural SnO2 growth templates.

13. 发明授权

US09559159B2 Low-temperature polysilicon membrane and preparation method thereof, thin-film transistor and display device 有权
标题翻译：低温多晶硅膜及其制备方法，薄膜晶体管及显示装置
公开(公告)号：US09559159B2
公开(公告)日：2017-01-31
申请号：US14421955
申请日：2014-04-23
申请人： BOE Technology Group Co., Ltd.
发明人： Huijuan Zhang
IPC分类号： H01L21/20 , H01L21/36 , H01L29/04 , H01L21/02 , H01L29/786 , H01L29/66
CPC分类号： H01L29/04 , H01L21/02422 , H01L21/02502 , H01L21/02532 , H01L21/02686 , H01L29/6675 , H01L29/786
摘要： A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S3) on a substrate (S1) by a patterning process, in which the a-Si layer (S3) comprises a plurality of convex structures (S32) and etched areas (S31) which are disposed along circumference of the plurality of convex structures and partially etched; and performing excimer laser crystallization (ELC) on the a-Si layer (S3) and obtaining the LTPS membrane. A thin-film transistor (TFT) and a display device are further disclosed, which are used for overcoming poor uniformity of the polysilicon membrane prepared by the ELC technology.
摘要翻译：一种制备LTPS膜的方法，包括：通过图案化工艺在衬底（S1）上形成非晶硅（a-Si）层（S3），其中a-Si层（S3）包括多个凸起结构（S32）和蚀刻区域（S31），它们沿着多个凸起结构的圆周设置并被部分蚀刻; 并在a-Si层（S3）上进行准分子激光结晶（ELC）并获得LTPS膜。进一步公开了薄膜晶体管（TFT）和显示装置，其用于克服由ELC技术制备的多晶硅膜的均匀性差。

14. 发明授权

US09530670B2 Methods of forming conductive patterns and methods of manufacturing semiconductor devices using the same using an etchant composition that includes phosphoric acid, nitric acid, and an assistant oxidant 有权
标题翻译：使用包括磷酸，硝酸和辅助氧化剂的蚀刻剂组合物来形成导电图案的方法和使用其制造半导体器件的方法
公开(公告)号：US09530670B2
公开(公告)日：2016-12-27
申请号：US14492122
申请日：2014-09-22
申请人： Samsung Electronics Co., Ltd. , Soulbrain Co., Ltd.
发明人： Hoon Han , Byoung-Moon Yoon , Young-Taek Hong , Keon-Young Kim , Jun-Youl Yang , Young-Ok Kim , Tae-Heon Kim , Sun-Joong Song , Jung-Hun Lim , Jae-Wan Park , Jin-Uk Lee
IPC分类号： H01L21/20 , H01L21/36 , H01L21/3213 , H01L29/423 , C09K13/04 , C23F1/26 , H01L21/321 , H01L27/115 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/32133 , C09K13/04 , C23F1/26 , H01L21/32115 , H01L21/32134 , H01L27/11582 , H01L29/4236 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.
摘要翻译：本公开内容涉及形成导电图案的方法以及使用其形成半导体器件的方法。在一些实施例中，形成导电图案的方法包括在衬底上形成第一导电层和第二导电层。第一导电层和第二导电层可以分别包括金属氮化物和金属。可以使用包括磷酸，硝酸，辅助氧化剂和剩余的水的蚀刻剂组合物来蚀刻第一导电层和第二导电层。蚀刻剂组合物可以具有与金属氮化物和金属基本相同的蚀刻速率。

15. 发明授权

US09490118B2 Method for manufacturing germanium epitaxial layer and method for manufacturing device using the same 有权
标题翻译：锗外延层的制造方法及其制造方法
公开(公告)号：US09490118B2
公开(公告)日：2016-11-08
申请号：US14642778
申请日：2015-03-10
申请人： UNITED MICROELECTRONICS CORP.
发明人： Jaw-Jyh Tseng , Chun-Ming Chen , Yao-Yi Huang
IPC分类号： H01L21/36 , H01L21/02 , H01L21/324
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02639 , H01L21/324 , H01L31/1075 , H01L31/1808 , H01L31/1864
摘要： A method for manufacturing a germanium (Ge) epitaxial layer is provided. First, a substrate is provided. Then, a first deposition process is performed to deposit a first Ge epitaxial film on the substrate. Next, a first annealing process is performed on the first Ge epitaxial film. Following that, a second deposition process is performed to directly deposit a second Ge epitaxial film on the first Ge epitaxial film. Thereafter, a second annealing process is performed on the second Ge epitaxial film, wherein the Ge epitaxial layer includes the first Ge epitaxial film and the second Ge epitaxial film, and a thickness of the Ge epitaxial layer is greater than 0.5 microns.
摘要翻译：提供了锗（Ge）外延层的制造方法。首先，提供基板。然后，执行第一沉积工艺以在衬底上沉积第一Ge外延膜。接下来，对第一Ge外延膜进行第一退火处理。之后，进行第二沉积工艺以在第一Ge外延膜上直接沉积第二Ge外延膜。此后，对第二Ge外延膜进行第二退火处理，其中Ge外延层包括第一Ge外延膜和第二Ge外延膜，Ge外延层的厚度大于0.5微米。

16. 发明授权

US09481929B2 Vapor deposition apparatus, vapor deposition method and method of manufacturing organic light emitting display apparatus 有权
标题翻译：蒸镀装置，蒸镀法及制造有机发光显示装置的方法
公开(公告)号：US09481929B2
公开(公告)日：2016-11-01
申请号：US14177180
申请日：2014-02-10
申请人： Samsung Display Co., Ltd.
发明人： Choel-Min Jang , Sung-Hun Key , In-Kyo Kim , Suk-Won Jung , Myung-Soo Huh
IPC分类号： H01L21/36 , C23C16/455
CPC分类号： C23C16/45551
摘要： A vapor deposition apparatus for depositing thin films on a substrate includes a supply unit including a plurality of linear supply members configured to supply at least one gas; and a nozzle unit including a plurality of nozzle members connected to the plurality of supply members and configured to supply the at least one gas toward the substrate, wherein two adjacent nozzle members of the plurality of nozzle members are connected to at least one common supply member of the plurality of supply members.
摘要翻译：一种用于在衬底上沉积薄膜的气相沉积设备包括：供给单元，包括多个线性供应构件，其被构造成供应至少一种气体; 以及喷嘴单元，其包括连接到所述多个供应构件并被配置为朝向所述基板供应所述至少一种气体的多个喷嘴构件，其中所述多个喷嘴构件中的两个相邻的喷嘴构件连接到至少一个共同的供应构件的多个供应构件。

17. 发明授权

US09472651B2 Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same 有权
标题翻译：具有降低的寄生电阻和电容的无隔离鳍片器件和制造相同的方法
公开(公告)号：US09472651B2
公开(公告)日：2016-10-18
申请号：US14017461
申请日：2013-09-04
申请人： GlobalFoundries U.S. 2 LLC
发明人： Effendi Leobandung
IPC分类号： H01L29/78 , H01L21/36 , H01L29/66 , H01L27/12 , H01L21/84 , H01L29/417
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66545
摘要： A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. A method to fabricate the structure is also disclosed.
摘要翻译：一种结构包括具有绝缘体层的衬底和设置在绝缘体层的表面上的多个细长的半导体鳍结构。翅片结构基本上彼此平行地设置。该结构还包括多个由氮化硅构成的细长的牺牲栅极结构。牺牲栅极结构彼此基本平行并且与多个翅片结构正交地布置，其中多个相邻翅片结构中的每一个的一部分嵌入在牺牲栅极结构之一内，而留下牺牲栅极结构之间的其它部分。该结构还包括多个半导体源极/漏极（S / D）结构，其设置在牺牲栅极结构之间的翅片结构的暴露部分之上。这些实施例消除了在翅片结构上形成常规间隔件的需要。还公开了制造该结构的方法。

18. 发明授权

US09460917B2 Method of growing III-N semiconductor layer on Si substrate 有权
标题翻译：在Si衬底上生长III-N半导体层的方法
公开(公告)号：US09460917B2
公开(公告)日：2016-10-04
申请号：US14179040
申请日：2014-02-12
申请人： Rytis Dargis , Andrew Clark , Nam Pham , Erdem Arkun
发明人： Rytis Dargis , Andrew Clark , Nam Pham , Erdem Arkun
IPC分类号： H01L21/20 , H01L21/36 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02433 , H01L21/02483 , H01L21/02488 , H01L21/02502 , H01L21/0254 , H01L21/02658 , H01L29/045 , H01L29/2003
摘要： A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single crystal silicon substrate and modifying the surface of the layer of epitaxial rare earth oxide with nitrogen plasma. The method further includes the steps of growing a layer of low temperature epitaxial gallium nitride on the modified surface of the layer of epitaxial rare earth oxide and growing a layer of bulk epitaxial III-N semiconductive material on the layer of low temperature epitaxial gallium nitride.
摘要翻译：一种在硅衬底上生长III-N半导体材料的方法，包括在单晶硅衬底上生长一层外延稀土氧化物并用氮等离子体改性外延稀土氧化物表面的步骤。该方法还包括以下步骤：在外延稀土氧化物层的改性表面上生长一层低温外延氮化镓，并在低温外延氮化镓层上生长一层体外延III-N半导体材料。

19. 发明授权

US09379132B2 NAND memory strings and methods of fabrication thereof 有权
标题翻译： NAND存储器串及其制造方法
公开(公告)号：US09379132B2
公开(公告)日：2016-06-28
申请号：US14523287
申请日：2014-10-24
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Raghuveer S. Makala , Yanli Zhang , Senaka Kanakamedala , Rahul Sharangpani , Yao-Sheng Lee , George Matamis
IPC分类号： G11C11/34 , H01L21/36 , H01L23/48 , H01L29/78 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
摘要翻译：制造单片三维存储器件的方法包括执行第一蚀刻以形成存储器开口和使用不同蚀刻工艺的第二蚀刻，以从存储器开口的底部去除半导体衬底的损坏部分。使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。另外的实施例包括提高存储器开口中的半导体沟道材料和底层半导体层之间的界面的质量，这可能被底部开口蚀刻损坏，包括通过从存储器的底表面的外延生长形成单晶半导体沟道材料暴露于底部开口蚀刻的开口和/或氧化表面，并在形成沟道材料之前去除氧化的表面。还公开了通过实施方式形成的单片三维存储器件。

20. 发明授权

US09373708B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09373708B2
公开(公告)日：2016-06-21
申请号：US14718763
申请日：2015-05-21
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shinya Sasagawa , Hitoshi Nakayama , Hiroshi Fujiki
IPC分类号： H01L29/786 , H01L21/336 , H01L21/36 , H01L29/66 , H01L27/12 , H01L21/02
CPC分类号： H01L29/66969 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L29/7869 , H01L29/78696
摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.
摘要翻译：为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层，除了含有氯的气体之外，还使用含有氧或氟的气体。

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