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11. 发明授权

US10862487B2 Locked loop circuit with reference signal provided by un-trimmed oscillator 有权
公开(公告)号：US10862487B2
公开(公告)日：2020-12-08
申请号：US16674207
申请日：2019-11-05
申请人： STMicroelectronics International N.V.
发明人： Anand Kumar , Nitin Gupta , Nitin Jain
IPC分类号： H03L1/00 , H03L7/183 , H03L7/087 , H03L7/085
摘要： A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

12. 发明授权

US10862486B2 All-digital phase locked loop using switched capacitor voltage doubler 有权
公开(公告)号：US10862486B2
公开(公告)日：2020-12-08
申请号：US16429774
申请日：2019-06-03
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
IPC分类号： H03L7/06 , H03L1/00 , G04F10/00 , H03L7/099 , H03L7/093 , H03L7/08
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

13. 发明授权

US10826429B2 Compensation module, oscillation circuit, and associated compensation method capable of reducing sensitivity of output oscillation signal 有权
公开(公告)号：US10826429B2
公开(公告)日：2020-11-03
申请号：US16172926
申请日：2018-10-29
申请人： MEDIATEK Inc.
发明人： Keng-Meng Chang , Yun-Chen Chuang , Yao-Chi Wang
IPC分类号： H03B5/12 , H03B5/04 , H03L7/099 , H03L1/00 , H02M3/158
摘要： A compensation module, an oscillation circuit and associated compensation method for reducing an oscillation frequency variation in an output oscillation signal of a voltage-controlled oscillator (VCO) core are provided. The compensation module includes a compensation circuit and a polarity selection circuit. The compensation circuit has a capacitance value related to voltages of a first and a second receiving terminals. The oscillation frequency variation is changed with the capacitance value. The polarity selection circuit conducts a periodic regulated signal to one of the first receiving terminal and the second receiving terminal. The polarity selection circuit conducts a filtered bias signal to the other of the first receiving terminal and the second receiving terminal. The periodic regulated signal is sensitive to a regulated voltage variation, and the filtered bias signal is insensitive to the regulated voltage variation.

14. 发明申请

US20200240819A1 SYSTEM AND METHOD FOR MEMS SENSOR SYSTEM SYNCHRONIZATION 审中-公开
公开(公告)号：US20200240819A1
公开(公告)日：2020-07-30
申请号：US16724815
申请日：2019-12-23
申请人： INVENSENSE, INC.
发明人： Andy Milota , James Lim , William Kerry Keal
IPC分类号： G01D18/00 , B81B7/02 , H03L1/00 , H03L7/00
摘要： Various aspects of this disclosure comprise systems and methods for synchronizing sensor data acquisition and/or output. For example, various aspects of this disclosure provide for achieving a desired level of timing accuracy in a MEMS sensor system, even in an implementation in which timer drift is substantial.

15. 发明授权

US10651854B2 Adaptive temperature compensation 有权
公开(公告)号：US10651854B2
公开(公告)日：2020-05-12
申请号：US15473112
申请日：2017-03-29
申请人： u-blox AG
发明人： Roderick Bryant , Eamonn Glennon
IPC分类号： H03L1/02 , H03B5/04 , G01S19/23 , H03L1/00
摘要： A method of compensating for the temperature related frequency drift of an oscillator. The method comprises using an external reference frequency signal to derive oscillator compensation data over a range of operating temperatures, storing the oscillator compensation data in a first table, and, for a given operating temperature, using the first table to obtain corresponding oscillator compensation data and applying that data to provide compensation for the temperature related frequency drift. The method further comprises defining, for the range of operating temperatures, a series of temperature slots each sub-divided into a series of temperature bins. The step of using an external reference frequency signal to derive oscillator compensation data over the range of operating temperatures comprises a) measuring an operating temperature and using the external reference frequency signal to determine oscillator compensation values for respective temperatures as the operating temperature varies; b) accumulating the determined oscillator compensation values in corresponding temperature bins of a second table; c) at spaced intervals in time, using the data accumulated in the temperature bins of the second table to determine or update the oscillator compensation data stored for one or more slots in the first table.

16. 发明申请

US20200136628A1 Signal Generator 审中-公开
公开(公告)号：US20200136628A1
公开(公告)日：2020-04-30
申请号：US16670394
申请日：2019-10-31
申请人： Stichting IMEC Nederland
发明人： Johan van den Heuvel , Paul Mateman
IPC分类号： H03L7/099 , H03M1/82 , H03L1/00
摘要： A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

17. 发明授权

US10615809B2 Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop 有权
公开(公告)号：US10615809B2
公开(公告)日：2020-04-07
申请号：US15718715
申请日：2017-09-28
申请人： STMicroelectronics International N.V.
发明人： Nitin Gupta , Ankit Gupta , Anand Kumar
IPC分类号： H03L7/099 , H03L1/00 , H03L7/18 , H03L7/22 , H03L7/087 , H03L7/093 , H03L7/089
CPC分类号： H03L7/099 , H03L1/00 , H03L7/087 , H03L7/18 , H03L7/22 , H03L7/0891 , H03L7/093 , H03L2207/05
摘要： Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.

18. 发明授权

US10573272B2 Device, method and system for providing a delayed clock signal to a circuit for latching data 有权
公开(公告)号：US10573272B2
公开(公告)日：2020-02-25
申请号：US16022357
申请日：2018-06-28
申请人： Intel Corporation
发明人： Christopher Mozak , Senthil Kumar Sampath
IPC分类号： H03L7/06 , G09G5/00 , H03K5/135 , H03K5/14 , H03L1/00 , H03L1/02 , H03L7/081 , H03K5/00
摘要： Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

19. 发明授权

US10461693B2 Circuit device, oscillator, electronic apparatus, and moving object 有权
公开(公告)号：US10461693B2
公开(公告)日：2019-10-29
申请号：US15345682
申请日：2016-11-08
申请人： Seiko Epson Corporation
发明人： Akihiro Fukuzawa
IPC分类号： G01N27/00 , G08B19/00 , G08B21/00 , G01J5/00 , G01K7/00 , G05D23/20 , G08B13/18 , G08B27/00 , H03B5/04 , H03B5/36 , H03L1/00 , H03L1/02
摘要： A circuit device includes an A/D conversion unit, a processing unit that performs a temperature compensation process of an oscillation frequency based on temperature detection data and outputs frequency control data of the oscillation frequency, a D/A conversion unit, and an oscillation circuit. The D/A conversion unit (area DAC) is disposed on a first direction DR1 side of the A/D conversion unit (area ADC). When a direction crossing the first direction DR1 is defined as a second direction DR2, the processing unit (area DSPL) is disposed on the second direction DR2 side of the A/D conversion unit and the D/A conversion unit. When a direction opposite to the second direction DR2 is defined as a third direction DR3, the oscillation circuit (area OSC) is disposed on the third direction DR3 side or the first direction DR1 side of the D/A conversion unit.

20. 发明授权

US10404258B2 Integrated circuit device having an injection-locked oscillator 有权
公开(公告)号：US10404258B2
公开(公告)日：2019-09-03
申请号：US15796608
申请日：2017-10-27
申请人： Rambus Inc.
发明人： Marko Aleksić , Brian S. Leibowitz
IPC分类号： H03B5/08 , H03B5/18 , H03L1/00 , H03L7/24 , H03K3/03 , H03L7/083
摘要： A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

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