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21. 发明授权

US08861278B2 Non-volatile memory device and cache program method of the same 有权
标题翻译：非易失性存储器件和缓存程序方法相同
公开(公告)号：US08861278B2
公开(公告)日：2014-10-14
申请号：US13291359
申请日：2011-11-08
申请人： You-Sung Kim , Se-Chun Park
发明人： You-Sung Kim , Se-Chun Park
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion.
摘要翻译：用于非易失性存储器件的缓存编程方法包括用于当前编程操作的编程数据到存储器单元阵列中，确定当前编程操作是否已经执行到程序完成的阈值点，以及接收用于下一个编程的数据当执行当前编程操作到程序完成的阈值点时的操作。

22. 发明授权

US08848469B2 Semiconductor device and testing method thereof 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US08848469B2
公开(公告)日：2014-09-30
申请号：US13333715
申请日：2011-12-21
申请人： Bo-Yeun Kim , Ji-Eun Jang
发明人： Bo-Yeun Kim , Ji-Eun Jang
IPC分类号： G11C29/00 , G11C29/44
CPC分类号： G11C29/785 , G11C29/802 , G11C2029/4402
摘要： A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.
摘要翻译：半导体器件分别包括响应于多个选择信号而被激活的多个单元块;预选择信号发生器，被配置为分别产生与单元块相对应的多个预选信号，并激活至少两个通过在多测试模式中解码地址来选择预选信号，选择信号控制器被配置为响应于多个预选信号选择性地激活多个选择信号，并且控制所激活的选择信号的有效期，以便不以及判定电路，其被配置为响应于所存储的修复信息和所述多个选择信号来确定响应于所激活的选择信号而被激活的单元块是否被修复。

23. 发明授权

US08846472B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08846472B2
公开(公告)日：2014-09-30
申请号：US13406739
申请日：2012-02-28
申请人： Hong-Gu Yi
发明人： Hong-Gu Yi
IPC分类号： H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10876
摘要： A method for fabricating a semiconductor device includes providing a substrate including first landing plugs and second landing plugs that are arrayed on a first line, forming a capping layer over the substrate, forming hole-type first trenches that expose the second landing plugs by selectively etching the capping layer, forming an insulation layer over the substrate including the first trenches, forming line-type second trenches that are stretched on the first line while overlapping with the first trenches by selectively etching the insulation layer, and forming a first conductive layer inside the second trenches.
摘要翻译：一种用于制造半导体器件的方法，包括提供包括排列在第一线上的第一着陆塞和第二着陆栓的衬底，在衬底上形成覆盖层，形成孔型第一沟槽，通过选择性蚀刻所述覆盖层在包括所述第一沟槽的所述衬底上形成绝缘层，形成线型第二沟槽，所述第二沟槽在所述第一线上被拉伸，同时通过选择性地蚀刻所述绝缘层而与所述第一沟槽重叠，以及在所述第一沟槽内部形成第一导电层第二壕沟

24. 发明授权

US08841198B2 Isolation layer having a bilayer structure for a semiconductor device and method for forming the same 有权
标题翻译：具有半导体器件的双层结构的隔离层及其形成方法
公开(公告)号：US08841198B2
公开(公告)日：2014-09-23
申请号：US12167322
申请日：2008-07-03
申请人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
发明人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
摘要翻译：本文描述了半导体器件的隔离层及其形成工艺。隔离层包括限定并形成在半导体衬底中的沟槽。第一衬里氮化物层形成在沟槽的表面上，并且在包括第一衬里氮化物层的沟槽中形成可流动的绝缘层。可流动绝缘层形成为在沟槽中限定凹部。在包括可流动绝缘层和第一衬里氮化物层的凹部上形成第二衬里氮化物层。最后，在第二衬里氮化物层上的凹槽中形成绝缘层以完全填充沟槽。

25. 发明授权

US08836410B2 Internal voltage compensation circuit 有权
标题翻译：内部电压补偿电路
公开(公告)号：US08836410B2
公开(公告)日：2014-09-16
申请号：US12215794
申请日：2008-06-30
申请人： Bong Hwa Jeong
发明人： Bong Hwa Jeong
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： H03K19/0185 , G11C5/143 , G11C5/147 , G11C11/4074 , H03K5/003
摘要： An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.
摘要翻译：提供内部电压补偿电路，其包括被配置为产生上电信号的上电信号发生器，选择信号发生器，被配置为将第一外部电压的电平与第二外部电压的电平进行比较，以产生第一和第二选择信号，其中响应于上电信号而产生第二选择信号;以及电压补偿单元，被配置为响应于第一和第二选择信号将内部电压电连接到第一外部电压或第二外部电压。

26. 发明授权

US08828864B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08828864B2
公开(公告)日：2014-09-09
申请号：US13279088
申请日：2011-10-21
申请人： Hyeong Uk Yun
发明人： Hyeong Uk Yun
IPC分类号： H01L21/4763 , H01L49/02 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： A semiconductor device and a method for manufacturing the same are disclosed. When forming a profile of the lower electrode, a second lower electrode hole (i.e., a bunker region) located at the lowermost part of the lower electrode is buried with an Ultra Low Temperature Oxide (ULTO) material without damaging the lower electrode material. As a result, when a dielectric film is deposited in a subsequent process, the above-mentioned semiconductor device prevents the occurrence of a capacitor leakage current caused by defective gapfilling of the dielectric film located at the lowermost part of the lower electrode.
摘要翻译：公开了一种半导体器件及其制造方法。当形成下电极的轮廓时，位于下电极的最下部的第二下电极孔（即，掩体区）用超低温氧化物（ULTO）材料掩埋，而不损坏下电极材料。结果，当在随后的工艺中沉积电介质膜时，上述半导体器件防止由于位于下电极的最下部的电介质膜的间隙填充而导致的电容器漏电流的发生。

27. 发明授权

US08823850B2 Image processing system with on-chip test mode for column ADCs 有权
标题翻译：具有片内ADC测试模式的图像处理系统
公开(公告)号：US08823850B2
公开(公告)日：2014-09-02
申请号：US12981970
申请日：2010-12-30
申请人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H04N5/335 , H03M1/10 , H04N5/228 , H04N17/00 , H04N5/378 , H04N5/374 , H03M1/56 , H03M1/12
CPC分类号： H04N5/374 , H03M1/1033 , H03M1/123 , H03M1/56 , H04N5/378 , H04N17/002
摘要： An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.
摘要翻译：图像处理系统包括：像素阵列，包括多个规则像素列和至少一个测试像素列;多个列模数转换器（ADC），被配置为对应于规则像素列并将模拟输入信号转换成数字信号和切换块，被配置为提供常规像素列的输出信号以在正常模式下输入相应的列ADC的端部，并且共同提供测试像素列的输出信号到列ADC的输入端在测试模式中，其中测试像素列产生具有不同于一行至另一行的微小电压的信号。

28. 发明授权

US08817555B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08817555B2
公开(公告)日：2014-08-26
申请号：US13478727
申请日：2012-05-23
申请人： Sung-Hwa Ok
发明人： Sung-Hwa Ok
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/109 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.
摘要翻译：半导体存储器件包括：内部信号生成单元，被配置为响应于外部地址输出列选择信号和写使能信号;写电路单元，被配置为响应于写使能信号输出与外部数据对应的内部数据，核心单元，被配置为响应于列选择信号来存储内部数据;以及输出定时控制单元，被配置为响应于外部命令来控制内部信号生成单元和写入电路单元的输出定时，内部同步信号和前导码相关信息。

29. 发明授权

US08780511B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08780511B2
公开(公告)日：2014-07-15
申请号：US13196258
申请日：2011-08-02
申请人： Jung-Eon Moon
发明人： Jung-Eon Moon
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0255 , H01L29/8611
摘要： An electrostatic discharge protection circuit includes a diode chain coupled between a power supply voltage end and a control node, a control voltage generator configured to generate a control voltage in response to a first current flowing through the diode chain, and a discharger configured to discharge a second current from the power supply voltage end to a ground voltage end in response to the control voltage, wherein the diode chain includes a plurality of P-well regions formed in an N-well region, diodes formed in the respective P-well regions, and a resistor coupled between the diodes.
摘要翻译：静电放电保护电路包括耦合在电源电压端和控制节点之间的二极管链，控制电压发生器，被配置成响应于流过二极管链的第一电流而产生控制电压;以及放电器，响应于所述控制电压从所述电源电压端到地电压端的第二电流，其中所述二极管链包括形成在N阱区中的多个P阱区，在所述P阱区中形成的二极管，和耦合在二极管之间的电阻器。

30. 发明授权

US08766708B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US08766708B2
公开(公告)日：2014-07-01
申请号：US13525805
申请日：2012-06-18
申请人： Jun-Gyu Lee
发明人： Jun-Gyu Lee
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.
摘要翻译：半导体器件包括内部电压输入缓冲器，其被配置为通过内部电压节点的电压电平与参考电压的电平之间的比较来确定上拉驱动节点和下拉驱动节点的电压电平电压节点，使得上拉驱动节点和下拉驱动节点保持电压电平差;以及内部电压驱动块，其被配置为响应于所述下拉驱动节点的电压电平上拉驱动内部电压节点，上拉驱动节点和下拉驱动内部电压节点响应于下拉驱动节点的电压电平。

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