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1. 发明授权

US09748003B2 Efficient coding for memory redundancy 有权
公开(公告)号：US09748003B2
公开(公告)日：2017-08-29
申请号：US14485379
申请日：2014-09-12
申请人： QUALCOMM Incorporated
发明人： Chulmin Jung , Sei Seung Yoon , Robert Henry Hoem
IPC分类号： G11C8/12 , G11C29/00 , G11C11/418 , G11C17/16 , G11C17/18 , G11C8/10
CPC分类号： G11C29/781 , G11C8/10 , G11C8/12 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/76 , G11C29/802 , G11C29/806
摘要： A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

2. 发明授权

US09727478B2 Apparatus and method for configurable redundant fuse banks 有权
公开(公告)号：US09727478B2
公开(公告)日：2017-08-08
申请号：US15209085
申请日：2016-07-13
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F13/12 , G06F12/0875 , G11C17/16 , G06F3/06 , G06F9/44 , G06F9/445 , G06F12/06 , G06F12/0806 , G11C17/18 , G11C29/00 , G06F11/10 , G06F12/0802 , G11C29/52 , G06F12/128 , G06F1/24 , G06F12/084 , G06F12/0811
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

3. 发明申请

US20160172058A1 SYSTEM AND METHOD FOR HANDLING MEMORY REPAIR DATA 有权
标题翻译：用于处理记忆修复数据的系统和方法
公开(公告)号：US20160172058A1
公开(公告)日：2016-06-16
申请号：US14568091
申请日：2014-12-11
申请人： Ankush Srivastava , Reinaldo Silveira
发明人： Ankush Srivastava , Reinaldo Silveira
IPC分类号： G11C29/44 , G11C16/10 , G11C15/04
CPC分类号： G11C29/4401 , G11C15/00 , G11C29/44 , G11C29/70 , G11C29/802 , G11C2029/4402
摘要： In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.
摘要翻译：在片上系统（SOC）设备中，即使某些存储器系统被门控（关闭）用于某些SOC配置，也提供了可由所有启用的存储器系统访问的存储器修复签名链的连续性。提供了用于在修复链内的压缩和未压缩存储器修复数据之间进行转换的机制，使得支持未压缩存储器修复数据（诸如三进制内容可寻址存储器）或压缩存储器修复数据的存储器系统可以被并入SOC中。

4. 发明申请

US20160078969A1 EFFICIENT CODING FOR MEMORY REDUNDANCY 有权
标题翻译：高效记忆冗余编码
公开(公告)号：US20160078969A1
公开(公告)日：2016-03-17
申请号：US14485379
申请日：2014-09-12
申请人： QUALCOMM Incorporated
发明人： Chulmin Jung , Sei Seung Yoon , Robert Henry Hoem
IPC分类号： G11C29/00 , G11C17/18 , G11C11/418 , G11C17/16
CPC分类号： G11C29/781 , G11C8/10 , G11C8/12 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/76 , G11C29/802 , G11C29/806
摘要： A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.
摘要翻译：可以提供为诸如SRAM之类的多个嵌入存储器提供冗余的系统。系统可以包括一个或多个解码器，每个解码器能够解码选择地址以识别嵌入存储器中的有缺陷的一个。

5. 发明授权

US09135969B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09135969B2
公开(公告)日：2015-09-15
申请号：US14299864
申请日：2014-06-09
申请人： SK hynix Inc.
发明人： Kwi-Dong Kim
IPC分类号： G11C29/44 , G11C7/22 , G11C17/16 , G11C29/02 , G11C29/00
CPC分类号： G11C7/222 , G11C17/16 , G11C29/027 , G11C29/44 , G11C29/4401 , G11C29/785 , G11C29/789 , G11C29/802 , G11C2029/4402
摘要： A semiconductor device may include a nonvolatile storage unit, a select signal generation unit suitable for generating a plurality of select signals using a clock, a plurality of storage units suitable for storing data transmitted from the nonvolatile storage unit in response to the plurality of select signals, respectively, and a clock blocking unit suitable for blocking the clock inputted to the select signal generation unit when the data transmitted from the nonvolatile storage unit is the same as the data stored in the plurality of storage units.
摘要翻译：半导体器件可以包括非易失性存储单元，适于使用时钟产生多个选择信号的选择信号生成单元，适于存储响应于多个选择信号从非易失性存储单元发送的数据的多个存储单元以及当从非易失性存储单元发送的数据与存储在多个存储单元中的数据相同时，适合于阻止输入到选择信号生成单元的时钟的时钟阻断单元。

6. 发明申请

US20150178103A1 APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA 有权
公开(公告)号：US20150178103A1
公开(公告)日：2015-06-25
申请号：US14635006
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. GLENN HENRY , DINESH K. JAIN
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

7. 发明申请

US20150135038A1 POST PACKAGE REPAIR OF MEMORY DEVICES 有权
标题翻译：邮件包修复记忆设备
公开(公告)号：US20150135038A1
公开(公告)日：2015-05-14
申请号：US14077630
申请日：2013-11-12
申请人： MICRON TECHNOLOGY, INC.
发明人： Alan J. Wilson , Jeffrey Wright
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C8/06 , G11C29/789 , G11C29/802 , G11C2029/4402
摘要： Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells.
摘要翻译：公开了用于后包装修复的装置和方法。装置可以包括封装中的存储器单元。存储元件可以存储响应于被激活的封装后修复模式的信息。信息可以标识映射到要修复的存储器单元的一部分的地址。存储元件可以响应于从包的节点接收的数据来存储信息。行走令牌电路可以响应于被激活的封装后修复模式，以串行方式询问存储在存储元件中的信息。映射电路可以根据询问将要修复的地址重新映射到存储器单元的另一部分。

8. 发明申请

US20150058564A1 APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 审中-公开
标题翻译：扩展高速缓存校正的设备和方法
公开(公告)号：US20150058564A1
公开(公告)日：2015-02-26
申请号：US13972481
申请日：2013-08-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F12/0802 , G06F3/0619 , G06F3/0632 , G06F3/0673 , G06F11/1008 , G06F15/76 , G11C29/787 , G11C29/802
摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.
摘要翻译：一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。半导体熔丝阵列设置在芯片上，其中编程了配置数据。半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。高速缓冲存储器设置在管芯上。多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

9. 发明申请

US20150055428A1 MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA 有权
标题翻译：用于解码缓存数据的微处理器机制
公开(公告)号：US20150055428A1
公开(公告)日：2015-02-26
申请号：US13972785
申请日：2013-08-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G11C17/16
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.
摘要翻译：一种装置具有熔丝阵列，高速缓冲存储器和核心。熔丝阵列设置在芯片上，其中编程了配置数据。熔丝阵列包括第一多个保险丝和第二多个保险丝。第一组多个保险丝存储压缩缓存校正数据。第二多个保险丝存储压缩的熔丝校正数据，该数据指示与其先前存储的状态将改变其状态的第一组多个保险丝内的一个或多个保险丝对应的位置和值。磁芯设置在芯片上，其中每个磁芯在上电/复位时访问熔丝阵列。每个核心包括高速缓存熔丝解压缩器，其根据位置和值改变状态，解压缩压缩高速缓存校正数据，并分配解压缩的高速缓存校正数据以初始化高速缓冲存储器。

10. 发明申请

US20140247679A1 SEMICONDUCTOR STORAGE DEVICE AND TESTING METHOD 审中-公开
标题翻译：半导体存储器件和测试方法
公开(公告)号：US20140247679A1
公开(公告)日：2014-09-04
申请号：US14277856
申请日：2014-05-15
申请人： FUJITSU LIMITED
发明人： Seiji Murata
IPC分类号： G11C29/12 , G11C29/00
CPC分类号： G11C29/12 , G11C7/10 , G11C11/41 , G11C29/04 , G11C29/24 , G11C29/70 , G11C29/802
摘要： A plurality of writing circuits respectively writes data to a plurality of memory cell arrays and a redundant cell array. A holding circuit, which is arranged for each memory cell array, holds data input as a storage target. A first selection circuit, which is arranged for each of the writing circuits of the memory cell arrays, selects data to be output to the writing circuits from among pieces of data input from the holding circuit of the memory cell array and holding circuits of other memory cell arrays. A switching circuit makes two or more first selection circuits select same data and to input the same data to three or more writing circuits so that the same data is written to two or more memory cell arrays and the redundant cell array when a prescribed signal becomes active.
摘要翻译：多个写入电路分别将数据写入多个存储单元阵列和冗余单元阵列。为每个存储单元阵列布置的保持电路保持输入的数据作为存储目标。为存储单元阵列的每个写入电路设置的第一选择电路从从存储单元阵列的保持电路输入的数据和其它存储器的保持电路中选择要输出到写入电路的数据单元阵列。开关电路使两个或多个第一选择电路选择相同的数据并将相同的数据输入到三个或更多个写入电路，使得当规定的信号变为有效时，将相同的数据写入两个或更多个存储单元阵列和冗余单元阵列。

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