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21. 发明授权

US08736042B2 Delamination resistant device package having raised bond surface and mold locking aperture 有权
标题翻译：具有升高的粘合表面和模具锁定孔的防分离装置包装
公开(公告)号：US08736042B2
公开(公告)日：2014-05-27
申请号：US13324749
申请日：2011-12-13
申请人： Felix C. Li , Yee Kim Lee , Peng Soon Lim , Terh Kuen Yii , Lee Han Meng@Eugene Lee
发明人： Felix C. Li , Yee Kim Lee , Peng Soon Lim , Terh Kuen Yii , Lee Han Meng@Eugene Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L23/495
CPC分类号： H01L23/49551 , H01L23/49503 , H01L23/49562 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49109 , H01L2224/49113 , H01L2224/49171 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/35121 , H01L2924/00011 , H01L2924/00013 , H01L2924/00 , H01L2224/85 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.
摘要翻译：一种半导体封装，其被配置为获得薄型和低湿度敏感性。本发明的封装可以包括安装在引线框架的管芯附接部位上的半导体管芯，并且还与围绕管芯附接焊盘布置并沿所述第一方向延伸的多个细长I / O引线连接。该引线框架具有一个“上部”焊盘，其布置有用于支撑多个引线接合的接合支撑件和在上压接焊盘中的大的模具流动孔。该包装封装在模制材料中，该模具材料围绕粘合支撑件并流过大型模具流动孔径以建立良好的支撑的线接合，使得该包装具有低湿度敏感性。

22. 发明授权

US08728920B2 Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the reverse breakdown 有权
标题翻译：具有控制栅极的肖特基二极管用于优化导通状态电阻，反向泄漏和反向击穿
公开(公告)号：US08728920B2
公开(公告)日：2014-05-20
申请号：US13486166
申请日：2012-06-01
申请人： Zia Alan Shafi , Jeffrey A. Babcock
发明人： Zia Alan Shafi , Jeffrey A. Babcock
IPC分类号： H01L21/425
CPC分类号： H01L29/7835 , H01L27/0629 , H01L29/0649 , H01L29/0692 , H01L29/872
摘要： A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
摘要翻译：肖特基二极管通过在位于肖特基二极管的金属 - 硅结和肖特基二极管的n +阴极接触之间的区域上形成绝缘控制栅极来优化肖特基二极管的导通状态电阻，反向漏电流和反向击穿电压肖特基二极管。

23. 发明授权

US08705253B2 Isolated SEPIC power converter for light emitting diodes and other applications 有权
标题翻译：用于发光二极管和其他应用的隔离SEPIC功率转换器
公开(公告)号：US08705253B2
公开(公告)日：2014-04-22
申请号：US13156086
申请日：2011-06-08
申请人： Jon R. Roman
发明人： Jon R. Roman
IPC分类号： H02M3/335
CPC分类号： H02M3/33523 , H02M2003/1557
摘要： A system includes a load and a single-ended primary-inductance converter (SEPIC) power converter configured to provide power to the load. The SEPIC power converter includes a primary side and a secondary side that are electrically isolated by a transformer. The transformer includes a primary coil and a secondary coil. The primary side includes (i) a capacitor coupled to a first end of the primary coil and (ii) an inductor and a switch coupled to a second end of the primary coil. The primary side of the SEPIC power converter could also include a diode coupled between the inductor and the switch, where the diode is coupled to the second end of the primary coil. The capacitor could be configured to transfer energy to the secondary side of the SEPIC power converter through the transformer during valleys associated with a rectified input voltage.
摘要翻译：一个系统包括负载和单端一次电感转换器（SEPIC）功率转换器，被配置为向负载提供电力。 SEPIC功率转换器包括由变压器电隔离的初级侧和次级侧。变压器包括初级线圈和次级线圈。初级侧包括（i）耦合到初级线圈的第一端的电容器和（ii）耦合到初级线圈的第二端的电感器和开关。 SEPIC功率转换器的初级侧还可以包括耦合在电感器和开关之间的二极管，其中二极管耦合到初级线圈的第二端。电容器可以被配置为在与整流输入电压相关的谷期间通过变压器将能量传递到SEPIC功率转换器的次级侧。

24. 发明授权

US08674418B2 Method and apparatus for achieving galvanic isolation in package having integral isolation medium 有权
标题翻译：用于在具有整体隔离介质的包装中实现电隔离的方法和装置
公开(公告)号：US08674418B2
公开(公告)日：2014-03-18
申请号：US13214069
申请日：2011-08-19
申请人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
发明人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
IPC分类号： H01L31/062 , H01L21/70 , H01L23/552
CPC分类号： H01F17/0013 , H01F27/32 , H01F27/36 , H01F2017/008
摘要： An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.
摘要翻译：描述了一种具有布置在一对线圈之间的改进的电隔离层和其构造方法的电感器件。

25. 发明授权

US08669157B2 Non-volatile memory cell having a heating element and a substrate-based control gate 有权
标题翻译：具有加热元件和基于基板的控制栅极的非易失性存储单元
公开(公告)号：US08669157B2
公开(公告)日：2014-03-11
申请号：US13477019
申请日：2012-05-21
申请人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
摘要翻译：可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。在编程和擦除之前，加热元件的热量时，编程和擦除电压也会降低。

26. 发明授权

US08665188B2 Laser diode / LED drive circuit 有权
标题翻译：激光二极管/ LED驱动电路
公开(公告)号：US08665188B2
公开(公告)日：2014-03-04
申请号：US12025526
申请日：2008-02-04
申请人： Yeong Ryong Yun
发明人： Yeong Ryong Yun
IPC分类号： G09G3/32 , G09G3/30
CPC分类号： H04N9/3161 , H04N9/3129
摘要： The invention relates to an apparatus for controlling the output of an LD or LED. The apparatus includes a substantially static bias source and a variable source. The substantially static bias source provides a bias current to the LD/LED. The variable source is capacitively coupled to the LD/LED. The bias current may be provided such that it is higher than a threshold current at which, when provided to an LD, lasing occurs.
摘要翻译：本发明涉及一种用于控制LD或LED的输出的装置。该装置包括基本上静态的偏置源和可变源。基本上静态的偏置源为LD / LED提供偏置电流。可变电源电容耦合到LD / LED。可以提供偏置电流，使得其高于在提供给LD时发生激光的阈值电流。

27. 发明授权

US08587268B1 System and method for providing an active current assist with analog bypass for a switcher circuit 有权
公开(公告)号：US08587268B1
公开(公告)日：2013-11-19
申请号：US12214280
申请日：2008-06-18
申请人： Jeffry Mark Huard
发明人： Jeffry Mark Huard
IPC分类号： G05F1/56 , G05F1/565 , G05F1/575
CPC分类号： H02M3/158 , H02M2003/1566
摘要： A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current assist circuit includes an active current analog bypass control circuit and a current source. The active current analog bypass control circuit receives and uses current limit information, voltage error information, and drop out information to determine a value of assist current that is appropriate for a current operational state of the buck regulator circuit. The active current analog bypass control circuit causes the current source to provide the appropriate value of assist current to the buck regulator circuit.

28. 发明授权

US08536679B2 High holding voltage BJT clamp with embedded reverse path protection in BCD process 有权
标题翻译：高保持电压BJT钳位在BCD工艺中具有嵌入式反向通路保护
公开(公告)号：US08536679B2
公开(公告)日：2013-09-17
申请号：US12807095
申请日：2010-08-27
申请人： Vladislav Vashchenko
发明人： Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/735 , H01L27/0259
摘要： In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.
摘要翻译：在其中一个节点被横向BJT钳位保护的相邻高压节点的情况下，通过增加基极接触区域来避免由于结构的两个相邻的高电压引脚之间的暂时闩锁引起的不可逆的烧坏，包括沉降片连接到基座。

29. 发明授权

US08531138B2 Dimmer decoder with improved efficiency for use with LED drivers 有权
标题翻译：调光解码器，提高了与LED驱动器使用的效率
公开(公告)号：US08531138B2
公开(公告)日：2013-09-10
申请号：US12904535
申请日：2010-10-14
申请人： Steven M. Barrow , James H. Masson , Daniel R. Herrington , Irwin R. Nederbragt , Chi Yuen Lai
发明人： Steven M. Barrow , James H. Masson , Daniel R. Herrington , Irwin R. Nederbragt , Chi Yuen Lai
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , H05B33/0845 , Y02B20/346
摘要： A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, sampling a subset of the pulses in the sense signal during that sampling period. The method further includes generating a holding current for the dimmer during the sampling of the subset of pulses in at least one of the sampling periods. In addition, the method includes, for each of the sampling periods, generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs). The subset of pulses in each of the sampling periods includes multiple pulses during that sampling period but not one or more initial pulses at a beginning of that sampling period.
摘要翻译：一种方法包括接收具有多个脉冲的感测信号，其中感测信号基于调光器的输出。对于多个采样周期中的每一个，该方法还包括在该采样周期期间对感测信号中的脉冲的子集进行采样。该方法还包括在至少一个采样周期中对脉冲子集进行采样期间产生用于调光器的保持电流。此外，对于每个采样周期，该方法包括产生识别用于驱动一个或多个发光二极管（LED）的占空比的输出值。每个采样周期中的脉冲子集在该采样周期期间包括多个脉冲，而在该采样周期的开始处不包括一个或多个初始脉冲。

30. 发明授权

US08502296B1 Non-volatile memory cell with asymmetrical split gate and related system and method 有权
标题翻译：具有不对称分裂门的非易失性存储单元及相关系统及方法
公开(公告)号：US08502296B1
公开(公告)日：2013-08-06
申请号：US12217539
申请日：2008-07-07
申请人： Andre P. Labonte , Jiankang Bu , Mark Rathmell
发明人： Andre P. Labonte , Jiankang Bu , Mark Rathmell
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.
摘要翻译：一种方法包括在半导体衬底上形成至少一个控制栅极。该方法还包括在至少一个控制栅极和半导体衬底上沉积一层导电材料。该方法还包括蚀刻导电材料层以形成与至少一个控制栅极相邻的多个间隔区，其中至少一个间隔物在至少一个存储单元中形成浮置栅极。可以在至少一个控制栅极附近形成两个间隔物，并且可以蚀刻一个间隔物，使得单个存储器单元包括控制栅极和剩余的间隔物。而且，可以与至少一个控制栅极相邻地形成两个间隔物，并且可以蚀刻和分离至少一个控制栅极以形成与不同存储器单元相关联的多个控制栅极。

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