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1. 发明授权

US08878295B2 DMOS transistor with a slanted super junction drift structure 有权
标题翻译：具有倾斜超结漂移结构的DMOS晶体管
公开(公告)号：US08878295B2
公开(公告)日：2014-11-04
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

2. 发明授权

US08785973B2 Ultra high voltage GaN ESD protection device 有权
标题翻译：超高压GaN ESD保护器件
公开(公告)号：US08785973B2
公开(公告)日：2014-07-22
申请号：US12799121
申请日：2010-04-19
申请人： Vladislav Vashchenko
发明人： Vladislav Vashchenko
IPC分类号： H01L29/20 , H01L21/335 , H01L29/778 , H01L27/02 , H01L29/861 , H01L29/205 , H01L29/06
CPC分类号： H01L29/861 , H01L27/0248 , H01L29/0657 , H01L29/2003 , H01L29/205
摘要： In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.
摘要翻译：在具有在两个端子之间延伸的2DEG区域的超高电压横向GaN结构中，在两个端子之间提供隔离区域以提供可逆的快速恢复。

3. 发明授权

US08536679B2 High holding voltage BJT clamp with embedded reverse path protection in BCD process 有权
标题翻译：高保持电压BJT钳位在BCD工艺中具有嵌入式反向通路保护
公开(公告)号：US08536679B2
公开(公告)日：2013-09-17
申请号：US12807095
申请日：2010-08-27
申请人： Vladislav Vashchenko
发明人： Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/735 , H01L27/0259
摘要： In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.
摘要翻译：在其中一个节点被横向BJT钳位保护的相邻高压节点的情况下，通过增加基极接触区域来避免由于结构的两个相邻的高电压引脚之间的暂时闩锁引起的不可逆的烧坏，包括沉降片连接到基座。

4. 发明申请

US20120091501A1 Low triggering voltage DIAC structure 有权
标题翻译：低触发电压DIAC结构
公开(公告)号：US20120091501A1
公开(公告)日：2012-04-19
申请号：US12925277
申请日：2010-10-18
申请人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
发明人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/87 , H01L27/0262 , H01L29/66121
摘要： In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
摘要翻译：在包括连接到高压节点的n +和p +区以及连接到低电压节点的n +和p +区的DIAC类器件中，在连接到低电压节点的n +和p +区之间形成至少两个MOS器件高压节点，连接到低电压节点的n +和p +区域。

5. 发明授权

US07839242B1 Magnetic MEMS switching regulator 有权
标题翻译：磁性MEMS开关调节器
公开(公告)号：US07839242B1
公开(公告)日：2010-11-23
申请号：US11893535
申请日：2007-08-16
申请人： Peter J. Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
发明人： Peter J. Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
IPC分类号： H01H51/34
CPC分类号： H02M3/34
摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
摘要翻译： MEMS磁通开关被制造为铁磁芯。芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。

6. 发明授权

US07800127B1 ESD protection device with controllable triggering characteristics using driver circuit related to power supply 有权
标题翻译：具有可控触发特性的ESD保护器件使用与电源相关的驱动电路
公开(公告)号：US07800127B1
公开(公告)日：2010-09-21
申请号：US11503593
申请日：2006-08-14
申请人： Vladislav Vashchenko , Alexander Burinskiy , Peter J. Hopper , Vladimir Kuznetsov
发明人： Vladislav Vashchenko , Alexander Burinskiy , Peter J. Hopper , Vladimir Kuznetsov
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/87
摘要： In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.
摘要翻译：在用于基于BSCR或NLDMOS-SCR的快速切换应用的ESD装置中，阳极结控制电极通过不将阳极电极连接到BSCR的集电极或NLDMOS-SCR的漏极而提供，并且阴极结通过在BSCR中的附加n +区域或NLDMOS-SCR的p阱中的附加p +区域形成控制电极。通过使用RC定时器驱动器电路控制一个或两个控制电极，在延迟之后调整ESD装置的触发电压。

7. 发明授权

US07795102B1 ESD high frequency diodes 有权
标题翻译： ESD高频二极管
公开(公告)号：US07795102B1
公开(公告)日：2010-09-14
申请号：US11654735
申请日：2007-01-17
申请人： Vladislav Vashchenko , Vladimir Kuznetsov , Peter J. Hopper
发明人： Vladislav Vashchenko , Vladimir Kuznetsov , Peter J. Hopper
IPC分类号： H01L21/331
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/161 , H01L29/66128
摘要： In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.
摘要翻译：在SiGe BJT工艺中，通过限定BJT集电极和BJT内部基极之间的pn结，形成二极管，阻挡BJT的外部栅极区域，并以与内部基底相同的掺杂剂类型掺杂BJT的发射极多晶，使用发射极接触来定义与内部基座的接触。通过子集电极或通过掺杂与收集器相同的掺杂剂类型的第二发射极多晶硅和内部基极建立与集电极的电接触。

8. 发明授权

US07521310B1 Vertical thyristor in complementary SiGe bipolar process 有权
标题翻译：互补SiGe双极工艺中的垂直晶闸管
公开(公告)号：US07521310B1
公开(公告)日：2009-04-21
申请号：US11261235
申请日：2005-10-29
申请人： Vladislav Vashchenko , Alexel Sadovnikov , Peter J. Hopper
发明人： Vladislav Vashchenko , Alexel Sadovnikov , Peter J. Hopper
IPC分类号： H01L21/8238
CPC分类号： H01L27/0817 , H01L21/8222 , H01L27/0641
摘要： In a complementary SiGe bipolar process, a pnpn thyristor structure is formed from some of the layers of a pnp transistor and an npn transistor formed on top of each other and making use of the SiGe gates to define the blocking junction.
摘要翻译：在互补的SiGe双极工艺中，pnpn晶闸管结构由形成在顶部上的pnp晶体管和npn晶体管的一些层形成，并且利用SiGe栅极来限定阻挡结。

9. 发明申请

US20080032467A1 Integrated Circuit with Metal Heat Flow Path Coupled to Transistor and Method for Manufacturing Such Circuit 有权
标题翻译：具有耦合到晶体管的金属热流路的集成电路及其制造方法
公开(公告)号：US20080032467A1
公开(公告)日：2008-02-07
申请号：US11869857
申请日：2007-10-10
申请人： Vladislav Vashchenko , Peter Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter Hopper , Yuri Mirgorodski
IPC分类号： H01L21/86
CPC分类号： H01L23/367 , H01L21/84 , H01L27/0211 , H01L27/12 , H01L27/1203 , H01L27/1207 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor) and methods for manufacturing such a chip. The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip. The chip can be an SOI chip including output circuitry and low-power circuitry, with at least one power transistor of the output circuitry, but no transistor of the low-power circuitry, having a terminal coupled to a metal heat flow path. Other embodiments are a chip including transistors and a feedback control loop coupled to at least one of the transistors for sensing temperature of the transistor and controlling at least one operating parameter of the transistor in response to the sensed temperature, and a method for manufacturing such chip.
摘要翻译：在一些实施例中，具有在其晶体管的端子和芯片的体半导体材料之间延伸的金属热流路的芯片（例如，从端子到其上形成晶体管的衬底或半导体器件的主体）与晶体管相邻）以及用于制造这种芯片的方法。该芯片可以通过半导体绝缘体（SOI）工艺来实现，并且可以包括至少一个双极或MOS晶体管，晶体管下面的绝缘体，绝缘体下面的半导体衬底，以及在绝缘体的端子之间延伸的金属热流路径晶体管通过绝缘体到基板。优选地，金属热流路径是通过对芯片的其他金属互连进行的相同类型的工艺步骤（或步骤）形成的金属互连。该芯片可以是包括输出电路和低功率电路的SOI芯片，其中至少一个输出电路的功率晶体管，但是没有低功率电路的晶体管具有耦合到金属热流路径的端子。其他实施例是包括晶体管和耦合到晶体管中的至少一个的反馈控制环路的芯片，用于感测晶体管的温度并且响应于感测到的温度控制晶体管的至少一个操作参数，以及用于制造这种芯片的方法。

10. 发明授权

US07285805B1 Low reference voltage ESD protection device 有权
标题翻译：低参考电压ESD保护器件
公开(公告)号：US07285805B1
公开(公告)日：2007-10-23
申请号：US11503594
申请日：2006-08-14
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L29/86 , H01L21/33 , H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436
摘要： In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.
摘要翻译：在低电压ESD保护器件中，通过不连接LVTSCR的n +漏极和p +发射极区域，并通过连接NMOS的二极管来控制控制电极，产生额外的控制电极。

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