会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 25. 发明申请
    • SIGE HBT HAVING A POSITION CONTROLLED EMITTER-BASE JUNCTION
    • SIGE HBT具有位置控制的发射器基座接点
    • US20130092981A1
    • 2013-04-18
    • US13613151
    • 2012-09-13
    • Feng HanDonghua LiuJun HuWenting DuanJing Shi
    • Feng HanDonghua LiuJun HuWenting DuanJing Shi
    • H01L29/737
    • H01L29/0817H01L29/1004H01L29/165H01L29/66242H01L29/7375
    • A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.
    • 公开了具有位置控制的发射极 - 基极结的SiGe HBT。 SiGe HBT包括:由N掺杂的有源区形成的集电极区域; 基底区域,形成在集电极区域上并且包括基底外延层,所述基底外延层包括SiGe层和形成在其上的覆盖层,所述SiGe层由掺杂有P型杂质的SiGe外延层形成,所述封盖 层掺杂有N型杂质; 以及形成在所述基极区上的发射极区域,所述发射极区域由多晶硅形成。 通过优化掺杂在基极区域中的杂质的分布,可以实现发射极 - 基极结的可控位置和其反向耐压的可调节性,从而提高了工艺的稳定性并提高了晶片内的均匀性。
    • 26. 发明授权
    • System and method for detection of multi-view/multi-pose objects
    • 用于检测多视点/多姿态对象的系统和方法
    • US08391592B2
    • 2013-03-05
    • US13134885
    • 2011-06-20
    • Feng HanYing ShanHarpreet Singh SawhneyRakesh Kumar
    • Feng HanYing ShanHarpreet Singh SawhneyRakesh Kumar
    • G06K9/62
    • G06K9/6256
    • The present invention provides a computer implemented process for detecting multi-view multi-pose objects. The process comprises training of a classifier for each intra-class exemplar, training of a strong classifier and combining the individual exemplar-based classifiers with a single objective function. This function is optimized using the two nested AdaBoost loops. The first loop is the outer loop that selects discriminative candidate exemplars. The second loop, the inner loop selects the discriminative candidate features on the selected exemplars to compute all weak classifiers for a specific position such as a view/pose. Then all the computed weak classifiers are automatically combined into a final classifier (strong classifier) which is the object to be detected.
    • 本发明提供了一种用于检测多视点多姿态对象的计算机实现过程。 该过程包括针对每个类内样本的分类器的训练,强分类器的训练和将单个基于样本的分类器与单个目标函数组合。 使用两个嵌套的AdaBoost循环来优化此功能。 第一个循环是选择区分候选样本的外循环。 第二个循环,内循环选择所选样本上的鉴别候选特征,以计算特定位置(例如视图/姿态)的所有弱分类器。 然后将所有计算的弱分类器自动组合成最终分类器(强分类器),该分类器是要检测的对象。
    • 30. 发明授权
    • Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same
    • 具有交替排列的P型和N型薄型半导体层的半导体器件及其制造方法
    • US08178409B2
    • 2012-05-15
    • US12832963
    • 2010-07-08
    • Shengan XiaoFeng Han
    • Shengan XiaoFeng Han
    • H01L29/15H01L21/336
    • H01L29/7802H01L21/2256H01L29/0634H01L29/086H01L29/66712
    • The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.
    • 本发明涉及具有交替排列的P型和N型薄型半导体层的半导体器件及其制造方法。 对于P型器件,该方法包括沟槽形成,沟槽侧壁上的热氧化物形成,沟槽中的N型硅形成,通过热氧化物的N型杂质扩散到P型外延层中,沟槽中的N型硅的氧化 和氧化物去除。 在半导体装置中,N型薄型半导体层通过氧化物的N型杂质扩散形成P型外延层,并且沟槽填充有氧化物。 通过这种方法,可以通过当前的大规模生产过程实现高压装置中相对低浓度的杂质,并且降低了器件开发成本和制造成本。