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21. 发明授权

US07123535B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07123535B2
公开(公告)日：2006-10-17
申请号：US11002245
申请日：2004-12-03
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C17/18
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

22. 发明授权

US09355719B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09355719B2
公开(公告)日：2016-05-31
申请号：US14415706
申请日：2012-07-19
申请人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
发明人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
IPC分类号： G11C8/00 , G11C13/00 , G06F12/02 , G11C29/24 , G11C29/04 , G11C16/04
CPC分类号： G11C13/0069 , G06F12/0246 , G06F2212/1008 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/0483 , G11C29/24 , G11C2029/0411 , G11C2213/72 , G11C2213/74 , G11C2213/75
摘要： A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.
摘要翻译：包括非易失性存储单元的半导体器件实现了可靠性和便利性的提高。半导体器件包括包括多个可重写存储单元（CL）的非易失性存储器单元和控制对非易失性存储器单元的访问的控制电路。例如，控制电路将一个物理地址分配给非易失性存储器单元中的链式存储器阵列CY。控制电路根据关于物理地址的第一写入命令，对链存储器阵列CY的分开的存储单元（例如CL0）进行写入，并对存储单元（例如CL1）进行写入，这是根据关于物理地址的第二写命令的另一部分。

23. 发明申请

US20150186056A1 STORAGE DEVICE SYSTEM 审中-公开
标题翻译：存储设备系统
公开(公告)号：US20150186056A1
公开(公告)日：2015-07-02
申请号：US14423384
申请日：2012-09-07
申请人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
发明人： Seiji Miura , Hiroshi Uchigaito , Kenzo Kurotsuchi
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/0652 , G06F3/0653 , G06F3/0659 , G06F3/0688 , G06F11/108
摘要： In a storage device system having a plurality of memory modules including a non-volatile memory, improved reliability and a longer life or the like is to be realized. To this end, a plurality of memory modules (STG) notifies a control circuit DKCTL0 of a write data volume (Wstg) that is actually written in an internal non-volatile memory thereof. The control circuit DKCTL0 finds a predicted write data volume (eWd) for each memory module on the basis of the write data volume (Wstg), a write data volume (Wh2d) involved in a write command that is already issued to the plurality of memory modules, and a write data volume (ntW) involved in a next write command. Then, a next write command is issued to the memory module having the smallest predicted write data volume.
摘要翻译：在具有包括非易失性存储器的多个存储器模块的存储设备系统中，将实现提高的可靠性和更长的使用寿命等。为此，多个存储器模块（STG）向控制电路DKCTL0通知实际写入其内部非易失性存储器的写入数据量（Wstg）。控制电路DKCTL0根据写入数据量（Wstg），已经发给多个存储器的写命令所涉及的写入数据量（Wh2d），找出每个存储器模块的预测写数据量（eWd）模块和下一个写命令中涉及的写数据卷（ntW）。然后，向具有最小预测写入数据量的存储器模块发出下一个写入命令。

24. 发明授权

US08618523B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08618523B2
公开(公告)日：2013-12-31
申请号：US12302740
申请日：2006-05-31
申请人： Norikatsu Takaura , Yuichi Matsui , Motoyasu Terao , Yoshihisa Fujisaki , Nozomu Matsuzaki , Kenzo Kurotsuchi , Takahiro Morikawa
发明人： Norikatsu Takaura , Yuichi Matsui , Motoyasu Terao , Yoshihisa Fujisaki , Nozomu Matsuzaki , Kenzo Kurotsuchi , Takahiro Morikawa
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
摘要翻译：在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52）引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程可以减小相变存储器的电压。

25. 发明授权

US08116128B2 Semiconductor device 有权
公开(公告)号：US08116128B2
公开(公告)日：2012-02-14
申请号：US12774476
申请日：2010-05-05
申请人： Riichiro Takemura , Kenzo Kurotsuchi , Takayuki Kawahara
发明人： Riichiro Takemura , Kenzo Kurotsuchi , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

26. 发明授权

US08000126B2 Semiconductor device with recording layer containing indium, germanium, antimony and tellurium 有权
标题翻译：具有含有铟，锗，锑和碲的记录层的半导体器件
公开(公告)号：US08000126B2
公开(公告)日：2011-08-16
申请号：US12522744
申请日：2007-01-11
申请人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki , Yoshihisa Fujisaki , Masaharu Kinoshita , Yuichi Matsui
发明人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki , Yoshihisa Fujisaki , Masaharu Kinoshita , Yuichi Matsui
IPC分类号： G11C11/00 , H01L29/66
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.
摘要翻译：相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在界面层和形成在记录层上的上接触电极。根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。

27. 发明申请

US20110049454A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110049454A1
公开(公告)日：2011-03-03
申请号：US12305890
申请日：2006-06-23
申请人： Motoyasu Terao , Yuichi Matsui , Tsuyoshi Koga , Nozomu Matsuzaki , Norikatsu Takaura , Yoshihisa Fujisaki , Kenzo Kurotsuchi , Takahiro Morikawa , Yoshitaka Sasago , Junko Ushiyama , Akemi Hirotsune
发明人： Motoyasu Terao , Yuichi Matsui , Tsuyoshi Koga , Nozomu Matsuzaki , Norikatsu Takaura , Yoshihisa Fujisaki , Kenzo Kurotsuchi , Takahiro Morikawa , Yoshitaka Sasago , Junko Ushiyama , Akemi Hirotsune
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.
摘要翻译：在相变存储器中，界面层插入硫族化物材料层和插塞之间。界面层被布置成不覆盖插塞状电极的整个界面。当塞子形成在比硫族化物层的上部时，积分度增加。通过使用氧化物靶进行溅射而形成界面层，或者通过使用金属靶进行溅射而形成金属膜，然后在氧自由基，氧等离子体等的氧化气氛中氧化金属膜。

28. 发明授权

US07796426B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07796426B2
公开(公告)日：2010-09-14
申请号：US12090375
申请日：2005-10-17
申请人： Osamu Tonomura , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki
发明人： Osamu Tonomura , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.
摘要翻译：一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

29. 发明申请

US20090302293A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090302293A1
公开(公告)日：2009-12-10
申请号：US12094403
申请日：2006-11-14
申请人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi
发明人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.
摘要翻译：在相同的半导体衬底1上，存储单元阵列，其中具有存储具有高电阻值的高电阻状态的硫族化物材料存储层22的多个存储元件R和具有低电阻的低电阻状态在存储单元区域mmry中形成以矩阵形式设置的原子排列变化的值，在逻辑电路区域lgc中形成半导体集成电路。该硫属化物材料储存层22由含有10.5原子％以上至40原子％以下的Ga或In中的至少任一种的硫属元素化物构成，5原子％以上且35原子％以下的Ge，Sb 为5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

30. 发明申请

US20090250680A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090250680A1
公开(公告)日：2009-10-08
申请号：US12487492
申请日：2009-06-18
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译：通过高速非易失性相变存储器，提高了刷新次数的可靠性。在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。

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