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21. 发明授权

US09343144B2 Memory device and method of controlling memory device 有权
公开(公告)号：US09343144B2
公开(公告)日：2016-05-17
申请号：US14810074
申请日：2015-07-27
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , H01L27/2454 , H01L27/249
摘要： According to one embodiment, a memory device includes a plurality of global column lines arranged in parallel and extending in a first direction; a plurality of row lines extending in a second direction which is perpendicular to the first direction; a plurality of column lines in a two-dimensional arrangement, which extend in a third direction which is perpendicular to the first direction and the second direction; and a memory cell array including a plurality of memory cells arranged at intersections between the row lines and the column lines.

22. 发明授权

US09324425B2 Memory device, method of controlling memory device, and memory system 有权
公开(公告)号：US09324425B2
公开(公告)日：2016-04-26
申请号：US14809703
申请日：2015-07-27
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00 , G11C7/10 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

23. 发明授权

US09123411B2 Memory device, method of controlling memory device, and memory system 有权
标题翻译：存储器件，存储器件控制方法和存储器系统
公开(公告)号：US09123411B2
公开(公告)日：2015-09-01
申请号：US14156595
申请日：2014-01-16
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.
摘要翻译：根据实施例的存储器件包括数据处理电路，其包括：数据写入预处理电路，其处理输入数据以产生第一中间数据; 数据写入处理电路，其基于所述第一中间数据顺序地设定所选行行与所选择的全局位线之间的电压差; 数据读取处理电路，其检测在所选择的全局位线中流动的电流或所选择的全局位线的电压，并从该检测结果顺序地生成第二中间数据; 以及数据读取后处理电路，其处理所述第二中间数据以产生输出数据，所述数据写入预处理电路和所述数据读取后处理电路具有校正功能，所述校正功能校正可能在所述输入数据和输出数据。

24. 发明授权

US08717840B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08717840B2
公开(公告)日：2014-05-06
申请号：US13773954
申请日：2013-02-22
申请人： Kabushiki Kaisha Toshiba
发明人： Yusuke Higashi , Haruki Toda , Kenichi Murooka , Satoru Takase , Yuichiro Mitani , Shuichi Toriyama
IPC分类号： G11C7/04
CPC分类号： G11C7/00 , G11C7/04 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C16/22 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.
摘要翻译：根据一个实施例，半导体存储器件包括包括块的存储单元阵列，每个块能够独立于其它块执行写入，读取或擦除操作。控制部分被配置为在第一周期中执行块中的第一块的操作，将选择禁止区域设置在距离第一块的预定距离的范围内，直到用于放宽第一块的温度的温度弛豫时间块已经过去，将除块中的选择禁止区域之外的区域设置为第二块，并且在第二周期中执行第二块的操作。

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