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1. 发明授权

US09293704B2 Memory device and method of manufacturing memory device 有权
公开(公告)号：US09293704B2
公开(公告)日：2016-03-22
申请号：US14592742
申请日：2015-01-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Murooka
IPC分类号： H01L45/00 , H01L27/24 , G11C13/00
CPC分类号： H01L45/1641 , G11C13/0002 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel.

2. 发明授权

US09224459B1 Memory device and method of initializing memory device 有权
标题翻译：存储器件和初始化存储器件的方法
公开(公告)号：US09224459B1
公开(公告)日：2015-12-29
申请号：US14017727
申请日：2013-09-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0083 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/145
摘要： According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit changing a condition of initialization of each of non-completed elements in which the initialization is not completed among the resistance change elements based on a number of completed elements in which the initialization is completed among the resistance change elements.
摘要翻译：根据一个实施例，存储器件包括连接在第一导线和第三导线一端之间的半导体层，分别连接在第二导线与第三导线之间的电阻变化元件，具有选择栅电极，并且使用半导体层作为通道，以及控制电路，其基于初始化为初始化的完成元件的数量，在电阻变化元件之间改变未完成初始化的每个未完成元件的初始化条件在电阻变化元素之间完成。

3. 发明授权

US09171615B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09171615B2
公开(公告)日：2015-10-27
申请号：US14334197
申请日：2014-07-17
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00 , G11C8/10 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
摘要翻译：根据一个实施例的半导体存储器件包括由多个行线和列线构成的存储单元阵列，所述多个行线和列线彼此相交，并且从布置在行线和列线的每个交点处的多个存储单元组成，并且每个包括可变电阻元件。在假设行数为N的情况下，假设列数为M，当存储单元中存在的一个存储单元中的电池电流为选择电压的一半时的电流比当将选择电压施加到一个存储器单元时，将存储单元中的一个施加到流过该存储单元中的一个存储单元的单元电流，则关系M2 <2×N×k 满意。

4. 发明授权

US09741766B2 Memory device 有权
公开(公告)号：US09741766B2
公开(公告)日：2017-08-22
申请号：US15152342
申请日：2016-05-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Murooka
IPC分类号： H01L27/24 , G11C5/06 , G11C5/02 , G11C13/00 , G11C7/10 , H01L21/768 , H01L29/66 , H01L45/00
CPC分类号： H01L27/2481 , G11C5/02 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/78 , H01L21/768 , H01L27/2454 , H01L29/66666 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

5. 发明授权

US09472283B2 Memory device having resistance change element and method of controlling the same 有权
标题翻译：具有电阻变化元件的存储器件及其控制方法
公开(公告)号：US09472283B2
公开(公告)日：2016-10-18
申请号：US14613837
申请日：2015-02-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0097 , G11C13/0069 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit executing a write/erase of at least one of the resistance change elements, and executing a recovering operation which adjusts a threshold voltage shift of the select FET after the write/erase.
摘要翻译：根据一个实施例，存储器件包括连接在第一导线和第三导线一端之间的半导体层，分别连接在第二导线与第三导线之间的电阻变化元件，具有选择栅电极，并且使用半导体层作为沟道，以及执行至少一个电阻变化元件的写入/擦除的控制电路，并且执行在写/擦除之后调节选择FET的阈值电压偏移的恢复操作。

6. 发明授权

US09209389B2 Memory device and fabricating method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US09209389B2
公开(公告)日：2015-12-08
申请号：US14038109
申请日：2013-09-26
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , H01L45/00 , H01L27/24 , G11C13/00
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.
摘要翻译：根据一个实施例，存储器件包括第一互连，第二互连和第一存储单元。第一存储器单元位于第一互连中的一个和第二互连中的一个的交叉点中。第一存储单元包括第一多层结构和第一可变电阻层，第一多层结构包括堆叠的第一电极，第一选择器和第一绝缘体。第一选择器和第一可变电阻层串联地电连接在第一互连和第二互连中的一个之间。第一可变电阻层形成在第一绝缘体的侧表面的一部分上以覆盖该部分而不覆盖剩余部分。

7. 发明授权

US08971093B2 Memory device and method of controlling memory device 有权
标题翻译：存储器件和控制存储器件的方法
公开(公告)号：US08971093B2
公开(公告)日：2015-03-03
申请号：US14025146
申请日：2013-09-12
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0097 , G11C13/0069 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit executing a write/erase of at least one of the resistance change elements, and executing a recovering operation which adjusts a threshold voltage shift of the select FET after the write/erase.
摘要翻译：根据一个实施例，存储器件包括连接在第一导线和第三导线一端之间的半导体层，分别连接在第二导线与第三导线之间的电阻变化元件，具有选择栅电极，并且使用半导体层作为沟道，以及执行至少一个电阻变化元件的写入/擦除的控制电路，并且执行在写/擦除之后调节选择FET的阈值电压偏移的恢复操作。

8. 发明授权

US08963115B2 Memory device and method of manufacturing memory device 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08963115B2
公开(公告)日：2015-02-24
申请号：US14017703
申请日：2013-09-04
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L45/1641 , G11C13/0002 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel.
摘要翻译：根据一个实施例，存储器件包括沿第一方向延伸的第一导电线，每条沿第二方向延伸的第二导线与第一方向交叉，第三导线沿着第三方向延伸，与第一和第二方向相交设置在所述第二导线和所述第三导线之间的绝缘层，电阻变化元件，其各自设置在所述第三方向上的每个所述第二导线的第一表面和所述第二表面中的一个上，并且各自连接到所述第三导电线，连接在第一导电线和第三导线的一端之间的半导体层，以及具有选择栅电极的选择FET，并且使用半导体层作为沟道。

9. 发明授权

US09721659B2 Memory device, method of controlling memory device, and memory system 有权
公开(公告)号：US09721659B2
公开(公告)日：2017-08-01
申请号：US15286711
申请日：2016-10-06
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00 , G11C7/10 , H01L45/00 , H01L27/24 , G06F3/06
CPC分类号： G11C13/0069 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G11C7/1006 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/16
摘要： A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

10. 发明授权

US09653684B2 Semiconductor memory device 有权
公开(公告)号：US09653684B2
公开(公告)日：2017-05-16
申请号：US14860805
申请日：2015-09-22
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Murooka
IPC分类号： H01L45/00 , H01L27/24 , G11C8/10 , G11C13/00
CPC分类号： H01L45/1233 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2

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