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21. 发明授权

US07652501B2 Programmable logic device structure using third dimensional memory 有权
标题翻译：使用第三维存储器的可编程逻辑器件结构
公开(公告)号：US07652501B2
公开(公告)日：2010-01-26
申请号：US12008077
申请日：2008-01-07
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F7/38
CPC分类号： H03K19/1776 , H03K19/17748 , H03K19/1778 , H03K19/17796
摘要： A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.
摘要翻译：公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。

22. 发明授权

US07593284B2 Memory emulation using resistivity-sensitive memory 有权
公开(公告)号：US07593284B2
公开(公告)日：2009-09-22
申请号：US11975275
申请日：2007-10-17
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C8/00
CPC分类号： G06F13/4239 , G06F13/1694 , G11C7/10 , G11C7/22 , Y02D10/14 , Y02D10/151
摘要： Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.

23. 发明申请

US20090174429A1 Programmable logic device structure using third dimensional memory 有权
标题翻译：使用第三维存储器的可编程逻辑器件结构
公开(公告)号：US20090174429A1
公开(公告)日：2009-07-09
申请号：US12008077
申请日：2008-01-07
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17748 , H03K19/1778 , H03K19/17796
摘要： A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.
摘要翻译：公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。

24. 发明申请

US20090164744A1 Memory access protection 审中-公开
标题翻译：内存访问保护
公开(公告)号：US20090164744A1
公开(公告)日：2009-06-25
申请号：US12004734
申请日：2007-12-24
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/14
CPC分类号： G06F21/79
摘要： A memory system is provided. The memory system includes a memory array and a memory controller in communication with the memory array. The memory controller is configured to receive a first password and to compare the first password with a second password. The second password is stored in the memory controller. If the first password matches the second password, then access is permitted to the memory array. The memory array can include a plurality of vertically stacked memory arrays. The vertically stacked memory arrays can be formed on top of a logic plane that includes active circuitry in communication with the vertically stacked memory arrays. The memory arrays can include two-terminal memory cells that store data as a plurality of conductivity profiles and retain the stored data in the absence of power. The memory arrays may be configured as non-volatile two-terminal cross-point memory arrays.
摘要翻译：提供了一种存储系统。存储器系统包括与存储器阵列通信的存储器阵列和存储器控制器。存储器控制器被配置为接收第一个密码并将第一个密码与第二个密码进行比较。第二个密码存储在内存控制器中。如果第一个密码与第二个密码匹配，则允许存储器阵列访问。存储器阵列可以包括多个垂直堆叠的存储器阵列。垂直堆叠的存储器阵列可以形成在包括与垂直堆叠的存储器阵列通信的有源电路的逻辑平面的顶部上。存储器阵列可以包括将数据存储为多个电导率分布并且在没有电力的情况下保存所存储的数据的两端存储器单元。存储器阵列可以被配置为非易失性两端交叉点存储器阵列。

25. 发明申请

US20090164204A1 Solid state drive with non-volatile memory for a media device 有权
标题翻译：用于介质设备的非易失性存储器的固态驱动器
公开(公告)号：US20090164204A1
公开(公告)日：2009-06-25
申请号：US12315292
申请日：2008-12-02
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F9/455
CPC分类号： G11C5/04 , G11C5/02
摘要： A media device is provided that includes a processor configured to execute a media device program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The non-volatile memory configured to emulate a hard disk drive. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication).
摘要翻译：提供了一种媒体设备，其包括被配置为执行媒体设备程序的处理器，与处理器电耦合的非易失性存储器，垂直配置的非易失性存储器，与处理器电耦合的输入/输出模块，并且被配置为与输入/输出设备进行通信，以及与处理器和非易失性存储器电耦合的模拟/数字模块，模拟/数字模块被配置为输出媒体信号。非易失性存储器配置为模拟硬盘驱动器。输入/输出模块可以与输入/输出设备（例如，电耦合）电连接和/或与输入/输出设备（例如，无线和/或光通信）的信号通信。

26. 发明申请

US20090106013A1 Memory emulation using resistivity-sensitive memory 有权
标题翻译：使用电阻率敏感记忆体的存储器仿真
公开(公告)号：US20090106013A1
公开(公告)日：2009-04-23
申请号：US11975275
申请日：2007-10-17
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F9/455
CPC分类号： G06F13/4239 , G06F13/1694 , G11C7/10 , G11C7/22 , Y02D10/14 , Y02D10/151
摘要： Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.
摘要翻译：公开了与至少一个非易失性电阻率敏感存储器通信的接口电路。存储器包括可以具有两个端子的多个非易失性存储器元件，其可操作以将数据存储为可以通过在存储器元件上施加读取电压来确定的多个导电率曲线，并且在不存在时保留存储的数据的权力。可以以交叉点阵列配置布置多个存储器元件。接口电路与例如DRAM，SRAM和FLASH等存储器类型的系统进行电气通信，并且可操作地与非易失性电阻率敏感存储器通信以模拟这些存储器类型中的一个或多个。接口电路可以在衬底上的逻辑平面中制造，其中至少一个非易失性电阻率敏感存储器垂直定位在逻辑平面上。非易失性电阻率敏感存储器可以彼此垂直堆叠。

27. 发明申请

US20060009708A1 Positive airway pressure system and method for treatment of sleeping disorder in patient 有权
标题翻译：积极的气道压力系统和治疗睡眠障碍的方法
公开(公告)号：US20060009708A1
公开(公告)日：2006-01-12
申请号：US11210568
申请日：2005-08-24
申请人： David Rapoport , Robert Norman
发明人： David Rapoport , Robert Norman
IPC分类号： A61M16/00 , A61B5/08
CPC分类号： A61B5/0816 , A61B5/0205 , A61B5/021 , A61B5/024 , A61B5/0476 , A61B5/087 , A61B5/4809 , A61B5/4818 , A61M16/0066 , A61M16/0069 , A61M16/024 , A61M16/06 , A61M2016/0021 , A61M2016/0039 , G06F19/00
摘要： Described are a positive airway pressure system and method for treatment of a sleeping disorder in a patient. The system includes a generator, a sensor and a processing arrangement. The generator supplies airflow and applies a pressure at to an airway of a patient. The sensor measures data corresponding to patient's breathing patterns. The processing arrangement analyzes the breathing patterns to determine whether the breathing patterns are indicative of at least one of the following patient's states: (i) a regular breathing state, (ii) a sleep disorder breathing state, (iii) a REM sleep state and (iv) a troubled wakefulness state. The processing arrangement adjusts the applied pressure as a function of the patient's state.
摘要翻译：描述了用于治疗患者睡眠障碍的正气道压力系统和方法。该系统包括发电机，传感器和处理装置。发电机提供气流并向患者的气道施加压力。传感器测量对应于患者呼吸模式的数据。处理装置分析呼吸模式以确定呼吸模式是否指示以下患者状态中的至少一个：（i）正常呼吸状态，（ii）睡眠障碍呼吸状态，（iii）REM睡眠状态和（iv）困扰的觉醒状态。处理装置根据病人的状态来调节施加的压力。

28. 发明申请

US20050268912A1 System and method for automated titration of continuous positive airway pressure 审中-公开
标题翻译：用于自动滴定持续气道正压的系统和方法
公开(公告)号：US20050268912A1
公开(公告)日：2005-12-08
申请号：US10862067
申请日：2004-06-04
申请人： Robert Norman , David Rapoport
发明人： Robert Norman , David Rapoport
IPC分类号： A61M16/00 , A61M16/10 , A62B7/00
CPC分类号： A61M16/10 , A61M16/0069 , A61M16/024 , A61M2016/0021 , A61M2016/0039
摘要： Described is a method and system for automated titration of CPAP. The system may include an air pressure supply providing air pressure to a patient's airways and a sensor detecting input data corresponding to a patient's breathing patterns of a plurality of breaths. The system also includes a titration device which receives and analyzes the input data to determine existence of breathing disorder and corresponding characteristics. The titration device generating output data for adjusting the air pressure supplied to the patient as a function of the characteristics of the breathing disorder.
摘要翻译：描述了一种自动滴定CPAP的方法和系统。该系统可以包括向患者的气道提供空气压力的气压供应器，以及检测与患者的多个呼吸的呼吸模式相对应的输入数据的传感器。该系统还包括滴定装置，其接收和分析输入数据以确定呼吸障碍和相应特征的存在。滴定装置产生用于根据呼吸障碍的特征调节供应给患者的气压的输出数据。

29. 发明授权

US08558574B2 Programmable logic device structure using third dimensional memory 有权
公开(公告)号：US08558574B2
公开(公告)日：2013-10-15
申请号：US13216052
申请日：2011-08-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17748 , H03K19/1778 , H03K19/17796
摘要： A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

30. 发明授权

US08456880B2 Multiple layers of memory implemented as different memory technology 失效
标题翻译：多层内存实现为不同的内存技术
公开(公告)号：US08456880B2
公开(公告)日：2013-06-04
申请号：US12653853
申请日：2009-12-18
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , Y10T29/4913
摘要： Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem.
摘要翻译：描述使用第三维存储器作为不同存储器技术的电路和方法。第三维存储器可用于特定应用的数据存储和/或仿真诸如DRAM，FLASH，SRAM和ROM之类的常规存储器类型，或者当新的存储器类型变得可用时。处理器存储器系统实现可操作为不同存储器技术的存储器。处理器存储器系统包括逻辑子系统和存储器子系统，其包括第三维存储器单元。逻辑子系统实现存储器技术特定的信号，以与第三维存储器单元作为不同存储器技术的存储器单元进行交互。因此，存储器子系统可以模拟不同的存储器技术。逻辑子系统可以在衬底上制造FEOL，并且存储器子系统可以直接在衬底的顶部上制造BEOL。层间互连结构可以将逻辑子系统与存储器子系统电耦合。

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