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1. 发明授权

US10660426B2 Electronic device harness assembly 有权
公开(公告)号：US10660426B2
公开(公告)日：2020-05-26
申请号：US16162554
申请日：2018-10-17
申请人： Robert Norman , Katrice Norman
发明人： Robert Norman , Katrice Norman
IPC分类号： A45F5/00 , F16M13/04 , A47B23/00 , A47B23/02
摘要： An electronic device harness assembly for facilitating hands-free use of an electronic device includes an electronic device that has a display. A harness is wearable over a user's shoulders a table is hingedly coupled to the harness. The table is positionable in a deployed position having the table being horizontally oriented. The electronic device is positionable on the table when the table is positioned in the deployed position. Thus, the display on the electronic device can be manipulated by the user when the user wears the harness.

2. 发明申请

US20200121065A1 ELECTRONIC DEVICE HARNESS ASSEMBLY 审中-公开
公开(公告)号：US20200121065A1
公开(公告)日：2020-04-23
申请号：US16162554
申请日：2018-10-17
申请人： Robert Norman , Katrice Norman
发明人： Robert Norman , Katrice Norman
IPC分类号： A45F5/00
摘要： An electronic device harness assembly for facilitating hands-free use of an electronic device includes an electronic device that has a display. A harness is wearable over a user's shoulders a table is hingedly coupled to the harness. The table is positionable in a deployed position having the table being horizontally oriented. The electronic device is positionable on the table when the table is positioned in the deployed position. Thus, the display on the electronic device can be manipulated by the user when the user wears the harness.

3. 发明授权

US08756158B2 Currency recycler 有权
标题翻译：货币回收商
公开(公告)号：US08756158B2
公开(公告)日：2014-06-17
申请号：US13618601
申请日：2012-09-14
申请人： Randy Colvin , Robert Norman , Jeffrey Siekman
发明人： Randy Colvin , Robert Norman , Jeffrey Siekman
IPC分类号： G06Q40/00
CPC分类号： G07D11/006 , G06Q20/1085 , G06Q40/00 , G07D11/0039 , G07D11/0057 , G07D11/0066 , G07D11/0072 , G07D11/0075 , G07D11/0081
摘要： A cash recycler that is configured to allow deposited money to be dispensed (recycled) in a withdrawal transaction. In one embodiment, multiple currency recyclers could be used at multiple stores of a retail establishment and collectively work from one pending balance. Embodiments are also contemplated in which multiple accounts at one recycler location. In some cases, the currency recycler provides provisional credit for deposits of coinage and checks. In some cases, transactions made on the currency recycler could be settled to any financial institution.
摘要翻译：一个现金回收商被配置为允许在提款交易中分配（回收）存入的货币。在一个实施例中，可以在零售企业的多个商店使用多个货币回收商，并且从一个待处理的余额中共同工作。也可以想到在一个回收站位置的多个账户的实施例。在某些情况下，货币回收商为存款和支票提供临时信贷。在某些情况下，货币回收商的交易可以结算到任何金融机构。

4. 发明授权

US08588005B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
公开(公告)号：US08588005B2
公开(公告)日：2013-11-19
申请号：US13455018
申请日：2012-04-24
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C16/04
CPC分类号： G11C7/1096 , G11C5/02 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C8/10 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C2013/0085 , G11C2013/0088 , G11C2213/71 , G11C2216/14
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

5. 发明授权

US08164656B2 Memory emulation in an image capture device 有权
标题翻译：图像捕获设备中的内存仿真
公开(公告)号：US08164656B2
公开(公告)日：2012-04-24
申请号：US11897726
申请日：2007-08-31
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H04N5/76 , G11C11/34 , G11C16/04
CPC分类号： H04N1/2166 , G11C13/00 , H04N2101/00 , H04N2201/216
摘要： An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, a non-volatile memory card, and FLASH memory, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the image capture device. At least one of the memory arrays may be in the form of a removable memory card.
摘要翻译：公开了使用直接寻址和非易失性的存储器阵列的图像捕获装置。存储器阵列可用于替代和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，非易失性存储卡和FLASH存储器。可以随机访问存储器阵列。存储在存储器阵列中的数据在没有电力的情况下被保留。在图像捕获装置中可以使用一个或多个存储器阵列。存储器阵列中的至少一个可以是可移动存储卡的形式。

6. 发明授权

US08120970B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
标题翻译：用于在集成电路中访问多层存储器的缓冲系统
公开(公告)号：US08120970B2
公开(公告)日：2012-02-21
申请号：US13134734
申请日：2011-06-14
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

7. 发明授权

US08120945B2 Preservation circuit and methods to maintain values representing data in one or more layers of memory 失效
标题翻译：保存电路和保持在一层或多层存储器中表示数据的值的方法
公开(公告)号：US08120945B2
公开(公告)日：2012-02-21
申请号：US12932637
申请日：2011-03-01
申请人： Christophe Chevallier , Robert Norman
发明人： Christophe Chevallier , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
摘要翻译：公开了用于恢复存储器中的数据的电路和方法。存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

8. 发明授权

US08020132B2 Combined memories in integrated circuits 有权
标题翻译：集成电路中的组合存储器
公开(公告)号：US08020132B2
公开(公告)日：2011-09-13
申请号：US12004292
申请日：2007-12-19
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F17/50
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.
摘要翻译：描述了集成电路中的组合存储器，包括确定对逻辑块的第一要求，确定包括用于存储器块的垂直配置的存储器块的第二要求，以及使用第一要求和第二要求编译集成电路的设计。存储器块可以包括非易失性两端交叉点存储器阵列。非易失性双端子交叉点存储器阵列可以形成在逻辑平面的顶部。逻辑平面可以在衬底中制造。非易失性双端子交叉点存储器阵列可以彼此垂直地堆叠以形成多个存储器平面。存储器平面可以分成子平面。可以通过多个存储器平面和/或子平面来仿真一个或多个不同的存储器类型，例如闪存，SRAM，DRAM和ROM。非易失性两端交叉点存储器阵列可以包括多个两端存储元件。

9. 发明授权

US08000122B2 Media player with non-volatile memory 有权
标题翻译：具有非易失性存储器的媒体播放器
公开(公告)号：US08000122B2
公开(公告)日：2011-08-16
申请号：US12803809
申请日：2010-07-06
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02
摘要： A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device and/or signal communication with the input/output device.
摘要翻译：提供一种媒体播放器，其包括被配置为执行媒体播放器程序的处理器，与处理器电耦合的非易失性存储器，垂直配置的非易失性存储器，与处理器电耦合的输入/输出模块，并且被配置为与输入/输出设备进行通信，以及与处理器和非易失性存储器电耦合的模拟/数字模块，模拟/数字模块被配置为输出媒体信号。输入/输出模块可以与输入/输出设备电连通和/或与输入/输出设备的信号通信。

10. 发明申请

US20110185116A1 Memory device with vertically embedded non-flash non-volatile memory for emulation of NAND flash memory 有权
公开(公告)号：US20110185116A1
公开(公告)日：2011-07-28
申请号：US13065823
申请日：2011-03-29
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C5/02 , G11C13/0002 , G11C16/102 , G11C16/16 , G11C2213/71 , Y02D10/13
摘要： A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.

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