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21. 发明申请

US20190158029A1 Gate Drivers for Stacked Transistor Amplifiers 审中-公开
公开(公告)号：US20190158029A1
公开(公告)日：2019-05-23
申请号：US16240601
申请日：2019-01-04
申请人： pSemi Corporation
发明人： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
IPC分类号： H03F1/02 , H03F1/22 , H03F3/193
摘要： Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

22. 发明申请

US20190121383A1 Controllable Temperature Coefficient Bias Circuit 审中-公开
公开(公告)号：US20190121383A1
公开(公告)日：2019-04-25
申请号：US15793943
申请日：2017-10-25
申请人： pSemi Corporation
发明人： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
IPC分类号： G05F3/26 , H03M1/66
CPC分类号： G05F3/262 , G05F3/242 , H03M1/66 , H03M1/742
摘要： A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

23. 发明授权

US10250199B2 Cascode amplifier bias circuits 有权
公开(公告)号：US10250199B2
公开(公告)日：2019-04-02
申请号：US15268229
申请日：2016-09-16
申请人： pSemi Corporation
发明人： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
IPC分类号： H03F1/02 , H03F1/22 , H03F1/30 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/24
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

24. 发明授权

US11614759B2 Leakage compensation circuit 有权
公开(公告)号：US11614759B2
公开(公告)日：2023-03-28
申请号：US17396508
申请日：2021-08-06
申请人： pSemi Corporation
发明人： Robert Mark Englekirk
IPC分类号： G05F1/56 , G05F1/565 , G05F3/26
摘要： Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

25. 发明授权

US11451205B2 Power amplifier self-heating compensation circuit 有权
公开(公告)号：US11451205B2
公开(公告)日：2022-09-20
申请号：US17124118
申请日：2020-12-16
申请人： pSemi Corporation
发明人： Tero Tapio Ranta , Keith Bargroff , Christopher C. Murphy , Robert Mark Englekirk
IPC分类号： H03F1/30 , H03F1/56 , H03F3/19 , H03F3/21 , H03G3/30 , H03F3/24
摘要： Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

26. 发明申请

US20220158589A1 Gate Drivers for Stacked Transistor Amplifiers 有权
公开(公告)号：US20220158589A1
公开(公告)日：2022-05-19
申请号：US17531510
申请日：2021-11-19
申请人： pSemi Corporation
发明人： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
IPC分类号： H03F1/02 , H03F3/193 , H03F1/22
摘要： Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

27. 发明申请

US20220021384A1 Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals 有权
公开(公告)号：US20220021384A1
公开(公告)日：2022-01-20
申请号：US17387469
申请日：2021-07-28
申请人： pSemi Corporation
发明人： Tero Tapio Ranta , Shawn Bawell , Robert W. Greene , Christopher N. Brindle , Robert Mark Englekirk
IPC分类号： H03K17/16 , H03M1/10 , H01F21/12 , H03H7/01 , H03K17/10 , H03K17/687 , H01G7/00 , H03H7/38 , H03H11/28 , H01L23/522 , H01L27/06 , H01L27/12 , H01L49/02 , H03J3/20 , H01G4/002
摘要： Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

28. 发明授权

US10775827B2 Controllable temperature coefficient bias circuit 有权
公开(公告)号：US10775827B2
公开(公告)日：2020-09-15
申请号：US15793943
申请日：2017-10-25
申请人： pSemi Corporation
发明人： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
IPC分类号： G05F3/26 , H03M1/66 , G05F3/24 , H03M1/74
摘要： A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

29. 发明授权

US10756678B2 Cascode amplifier bias circuits 有权
公开(公告)号：US10756678B2
公开(公告)日：2020-08-25
申请号：US16250889
申请日：2019-01-17
申请人： pSemi Corporation
发明人： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
IPC分类号： H03F1/22 , H03F3/195 , H03F3/213 , H03F3/24 , H03F1/30 , H03F1/56 , H03F3/193
摘要： Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

30. 发明申请

US20190025863A1 Low-Noise High Efficiency Bias Generation Circuits and Method 审中-公开
公开(公告)号：US20190025863A1
公开(公告)日：2019-01-24
申请号：US16143142
申请日：2018-09-26
申请人： pSemi Corporation
发明人： Tae Youn Kim , Robert Mark Englekirk
IPC分类号： G05F1/56 , H03F1/30 , G05F1/46
CPC分类号： G05F1/56 , G05F1/468 , H03F1/303
摘要： Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

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